On Wed, Jun 03, 2020 at 08:15:44PM +0200, Patrick Wildt wrote:
> On Wed, Jun 03, 2020 at 04:27:00PM +0100, Steve wrote:
> > A pair of us have been using OpenBSB as our firewall for about 10
> > years now, but the hardware is getting old and we want to replace
> > it with a smaller / lower power device. With the new Arm boards out
> > now we have been attempting to make a new version using the Nano Pi
> > R2S from FriendlyElec which appears to be perfect, but we are not
> > experienced in getting Arm SBC's working with OpenBSD.
> >
> > The R2S is an RK3328 based dual ethernet SBC and we have taken the
> > rk3328-roc-cc.dts (Firefly board) as a base to modify, and compiled
> > u-boot, with bl31 to get OpenBSD installed and running, as well as
> > comparing the similar schematics.
> >
> > After OpenBSD boots, one of the ethernet ports which we believe to
> > be connected directly to the RockChip is detected, giving a dwge0
> > device, but the second ethernet port is not detected at all.
> >
> > From looking at the schematic diagram we think that the RTL8153 IC
> > is connected via USB3.0 interface and we are not getting any USB3.0
> > show up in the dmesg log.
> >
> > If were configured correctly, we think that we would expect to see a
> > ure0 device. So this configuration needs to be added to the device
> > tree.
> >
> > There is a working linux Armbian image which when checked allows
> > access to both LAN ports. Converting their dtb->dts, there is a
> > section for usb at 0xff6000000, which matches the RK3328 data sheet
> > memory map for the USB3 register set.
> >
> > This, and the subsection dwc3, which we believe uses the phy's
> > referenced as utmi and pipe, have many sections, such as the clocks,
> > resets (and interrupts?) for which we can find no relevant information.
> >
> > Also of note is that on the schematic for the board, the pin GPIO2_C6
> > seems to be required to be high to enable power to the USB subsystem,
> > as VDD_5V_LAN powers the IO of the RTL8153 device.
> >
> > Further, the WAN-LED / LAN-LED from pins GPIO2_C2 / GPIO2_B7 remain
> > off and unconfigured from the boot output even when we have attempted
> > to direct them to be on.
> >
> > What are we are doing wrong in order to develop the dts to a working
> > state? Any pointers to information on how to proceed and verify our
> > progress would be appreciated. Especially, how do we set IO lines
> > high so that we may power the USB3.0 subsystem and RTL8153 ?
> >
> >
> > The defconfig is again based on the roc-cc one and contains:
> >
> > CONFIG_USB=y
> > CONFIG_USB_XHCI_HCD=y
> > CONFIG_USB_XHCI_DWC3=y
> > CONFIG_USB_EHCI_HCD=y
> > CONFIG_USB_EHCI_GENERIC=y
> > CONFIG_USB_OHCI_HCD=y
> > CONFIG_USB_OHCI_GENERIC=y
> > CONFIG_USB_DWC2=y
> > CONFIG_USB_DWC3=y
> > # CONFIG_USB_DWC3_GADGET is not set
> > CONFIG_USB_GADGET=y
> > CONFIG_USB_GADGET_DWC2_OTG=y
> >
> > Also, relevant sections of our dts file are shown below.
> >
> > Many thanks.
> >
> > syscon: syscon@ff460000 {
> > compatible = "rockchip,usb3phy-grf", "syscon";
> > reg = <0x0 0xff460000 0x0 0x1000>;
> > };
> >
> > u3phy: u3phy@ff470000 {
> > compatible = "rockchip,rk3328-u3phy";
> > reg = <0x0 0xff470000 0x0 0x0>;
> > rockchip,u3phygrf = <&syscon>;
> > rockchip,grf = <&grf>;
> > interrupts = <0x0 0x4d 0x4>;
> > interrupt-names = "linestate";
> > clocks = <0x2 0xe0 0x2 0xe1>;
> > clock-names = "u3phy-otg", "u3phy-pipe";
> > resets = <0x2 0x7d 0x2 0x7e 0x2 0x7f 0x2 0x7c 0x2 0x9e 0x2 0x9f>;
> > reset-names = "u3phy-u2-por", "u3phy-u3-por", "u3phy-pipe-mac",
> > "u3phy-utmi-mac", "u3phy-utmi-apb", "u3phy-pipe-apb";
> > #address-cells = <0x2>;
> > #size-cells = <0x2>;
> > ranges;
> > status = "okay";
> >
> > utmi: utmi@ff470000 {
> > reg = <0x0 0xff470000 0x0 0x8000>;
> > #phy-cells = <0x0>;
> > status = "okay";
> > };
> >
> > pipe: pipe@ff478000 {
> > reg = <0x0 0xff478000 0x0 0x8000>;
> > #phy-cells = <0x0>;
> > status = "okay";
> > };
> > };
> >
> > usb30: usb@ff600000 {
> > compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
> > clocks = <0x2 0x60 0x2 0x84 0x2 0x61>; // Should contain &u3phy?
> > // Are some phandles?
> > clock-names = "ref", "bus_early", "suspend";
> > #address-cells = <0x2>;
> > #size-cells = <0x2>;
> > ranges;
> > clock-ranges;
> > status = "okay";
> > phy-supply = <&vcc_usb30>;
> >
> > dwc3@ff600000 {
> > compatible = "snps,dwc3";
> > reg = <0x0 0xff600000 0x0 0x100000>;
> > interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; // OK?
> > dr_mode = "host";
> > phys = <&utmi &pipe>;
> > phy-names = "u2phy", "u3phy";
> > phy_type = "utmi_wide";
> > snps,dis_enblslpm_quirk;
> > snps,dis-u2-freeclk-exists-quirk;
> > snps,dis_u2_susphy_quirk;
> > snps,dis_u3_susphy_quirk;
> > snps,dis-del-phy-power-chg-quirk;
> > snps,dis-tx-ipgap-linecheck-quirk;
> > snps,xhci-trb-ent-quirk;
> > status = "okay";
> > #address-cells = <0x1>;
> > #size-cells = <0x0>;
> >
> > device@2 {
> > compatible = "usbbda:8153";
> > reg = <0x2>;
> > local-mac-address = [00 00 00 00 00 00];
> > };
> > };
> > };
> >
> > vcc-sys {
> > compatible = "regulator-fixed";
> > regulator-name = "vcc_usb30";
> > regulator-always-on;
> > regulator-boot-on;
> > gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
> > pinctrl-names = "default";
> > pinctrl-0 = <&i2s1_sdio3>;
> > regulator-min-microvolt = <5000000>;
> > regulator-max-microvolt = <5000000>;
> > vin-supply = <&vcc_io>;
> > };
> >
> > leds_all: leds {
> > compatible = "gpio-leds";
> >
> > status {
> > label = "r2s:red:status";
> > linux,default-trigger = "heartbeat";
> > gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
> > default-state = "on";
> > };
> >
> > wan {
> > label = "r2s:green:wan";
> > gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
> > default-state = "on";
> > };
> >
> > lan {
> > label = "r2s:green:lan";
> > gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
> > default-state = "on";
> > };
> > };
> >
> > &vcc_usb30 {
> > status = "okay";
> > };
> >
> > &leds_all {
> > status = "okay";
> > };
> >
>
> About 6 weeks ago I build my own U-Boot for the R2S, based on what's in
> U-Boot master, and also built a device tree based on Linux master, I
> think, and also the patches in FriendlyARM's repo. Here's the DTB,
> put this onto your MS-DOS partition and make sure that U-Boot loads
> that file (and not something else).
>
> The u-boot environment contains an fdtfile or fdt_file variable. You
> can either change that variable to reflect the filename, or you can
> put the file onto the MS-DOS partition with the name as in the variable.
>
> Patrick
This is the diff I had in sysutils/dtb, but that was based on the 5.6
port and the port is now using 5.7.
diff --git
a/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328-nanopi-r2-common_dtsi
b/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328-nanopi-r2-common_dtsi
new file mode 100644
index 00000000000..e3e1dc521fd
--- /dev/null
+++
b/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328-nanopi-r2-common_dtsi
@@ -0,0 +1,547 @@
+$OpenBSD$
+
+Index: arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi
+--- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi.orig
++++ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi
+@@ -0,0 +1,541 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
++ */
++
++/dts-v1/;
++#include "rk3328.dtsi"
++
++/ {
++ model = "FriendlyElec boards based on Rockchip RK3328";
++ compatible = "friendlyelec,nanopi-r2",
++ "rockchip,rk3328";
++
++ chosen {
++ stdout-path = "serial2:115200n8";
++ };
++
++ gmac_clkin: external-gmac-clock {
++ compatible = "fixed-clock";
++ clock-frequency = <125000000>;
++ clock-output-names = "gmac_clkin";
++ #clock-cells = <0>;
++ };
++
++ mach: board {
++ compatible = "friendlyelec,board";
++ machine = "NANOPI-R2";
++ hwrev = <255>;
++ model = "NanoPi R2 Series";
++ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
++ nvmem-cell-names = "id", "cpu-version";
++ };
++
++ leds: gpio-leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 =<&leds_gpio>;
++ status = "disabled";
++
++ led@1 {
++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
++ label = "status_led";
++ linux,default-trigger = "heartbeat";
++ linux,default-trigger-delay-ms = <0>;
++ };
++ };
++
++ sdio_pwrseq: sdio-pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ clocks = <&rk805 1>;
++ clock-names = "ext_clock";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_enable_h>;
++
++ /*
++ * On the module itself this is one of these (depending
++ * on the actual card populated):
++ * - SDIO_RESET_L_WL_REG_ON
++ * - PDN (power down when low)
++ */
++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
++ };
++
++ sdmmc_ext: dwmmc@ff5f0000 {
++ compatible = "rockchip,rk3328-dw-mshc",
"rockchip,rk3288-dw-mshc";
++ reg = <0x0 0xff5f0000 0x0 0x4000>;
++ clock-freq-min-max = <400000 150000000>;
++ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
++ <&cru SCLK_SDMMC_EXT_DRV>, <&cru
SCLK_SDMMC_EXT_SAMPLE>;
++ clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
++ fifo-depth = <0x100>;
++ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++
++ vcc_sd: sdmmc-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0m1_gpio>;
++ regulator-name = "vcc_sd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_io>;
++ };
++
++ vccio_sd: sdmmcio-regulator {
++ compatible = "regulator-gpio";
++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
++ states = <1800000 0x1
++ 3300000 0x0>;
++ regulator-name = "vccio_sd";
++ regulator-type = "voltage";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ vin-supply = <&vcc_io>;
++ startup-delay-us = <2000>;
++ regulator-settling-time-us = <5000>;
++ enable-active-high;
++ status = "disabled";
++ };
++
++ vcc_sys: vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc_phy: vcc-phy-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_phy";
++ regulator-always-on;
++ regulator-boot-on;
++ };
++
++ vcc_host_vbus: host-vbus-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_host_vbus";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&emmc {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ max-frequency = <150000000>;
++ mmc-hs200-1_8v;
++ no-sd;
++ non-removable;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
++ vmmc-supply = <&vcc_io>;
++ vqmmc-supply = <&vcc18_emmc>;
++ status = "okay";
++};
++
++&gmac2phy {
++ phy-supply = <&vcc_phy>;
++ clock_in_out = "output";
++ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
++ assigned-clock-rate = <50000000>;
++ assigned-clocks = <&cru SCLK_MAC2PHY>;
++ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
++ status = "disabled";
++};
++
++&gmac2io {
++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
++ clock_in_out = "input";
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmiim1_pins>;
++ phy-handle = <&rtl8211e>;
++ phy-mode = "rgmii";
++ phy-supply = <&vcc_phy>;
++ snps,reset-active-low;
++ snps,reset-delays-us = <0 10000 30000>;
++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ snps,aal;
++ snps,rxpbl = <0x4>;
++ snps,txpbl = <0x4>;
++ tx_delay = <0x24>;
++ rx_delay = <0x18>;
++ status = "okay";
++
++ mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtl8211e: phy@0 {
++ reg = <0>;
++ reset-assert-us = <10000>;
++ reset-deassert-us = <30000>;
++ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
++ };
++ };
++};
++
++&i2c1 {
++ status = "okay";
++
++ rk805: rk805@18 {
++ compatible = "rockchip,rk805";
++ reg = <0x18>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ clock-output-names = "xin32k", "rk805-clkout2";
++ gpio-controller;
++ #gpio-cells = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int_l>;
++ rockchip,system-power-controller;
++ wakeup-source;
++
++ vcc1-supply = <&vcc_sys>;
++ vcc2-supply = <&vcc_sys>;
++ vcc3-supply = <&vcc_sys>;
++ vcc4-supply = <&vcc_sys>;
++ vcc5-supply = <&vcc_io>;
++ vcc6-supply = <&vcc_io>;
++
++ regulators {
++ vdd_logic: DCDC_REG1 {
++ regulator-name = "vdd_logic";
++ regulator-init-microvolt = <1075000>;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++
++ vdd_arm: DCDC_REG2 {
++ regulator-name = "vdd_arm";
++ regulator-init-microvolt = <1225000>;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <950000>;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_io: DCDC_REG4 {
++ regulator-name = "vcc_io";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc_18: LDO_REG1 {
++ regulator-name = "vcc_18";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc18_emmc: LDO_REG2 {
++ regulator-name = "vcc18_emmc";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_10: LDO_REG3 {
++ regulator-name = "vdd_10";
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++ };
++ };
++};
++
++&io_domains {
++ status = "okay";
++
++ vccio1-supply = <&vcc_io>;
++ vccio2-supply = <&vcc18_emmc>;
++ vccio3-supply = <&vcc_io>;
++ vccio4-supply = <&vcc_io>;
++ vccio5-supply = <&vcc_io>;
++ vccio6-supply = <&vcc_18>;
++ pmuio-supply = <&vcc_io>;
++};
++
++&pinctrl {
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ sdio-pwrseq {
++ wifi_enable_h: wifi-enable-h {
++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ sdmmc0 {
++ sdmmc0_clk: sdmmc0-clk {
++ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
++ };
++
++ sdmmc0_cmd: sdmmc0-cmd {
++ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
++ };
++
++ sdmmc0_dectn: sdmmc0-dectn {
++ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
++ };
++
++ sdmmc0_bus4: sdmmc0-bus4 {
++ rockchip,pins =
++ <1 RK_PA0 1 &pcfg_pull_up_4ma>,
++ <1 RK_PA1 1 &pcfg_pull_up_4ma>,
++ <1 RK_PA2 1 &pcfg_pull_up_4ma>,
++ <1 RK_PA3 1 &pcfg_pull_up_4ma>;
++ };
++ };
++
++ sdmmc0ext {
++ sdmmc0ext_clk: sdmmc0ext-clk {
++ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>;
++ };
++
++ sdmmc0ext_cmd: sdmmc0ext-cmd {
++ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>;
++ };
++
++ sdmmc0ext_bus4: sdmmc0ext-bus4 {
++ rockchip,pins =
++ <3 RK_PA4 3 &pcfg_pull_up_2ma>,
++ <3 RK_PA5 3 &pcfg_pull_up_2ma>,
++ <3 RK_PA6 3 &pcfg_pull_up_2ma>,
++ <3 RK_PA7 3 &pcfg_pull_up_2ma>;
++ };
++ };
++
++ gmac-1 {
++ rgmiim1_pins: rgmiim1-pins {
++ rockchip,pins =
++ /* mac_txclk */
++ <1 RK_PB4 2 &pcfg_pull_none_4ma>,
++ /* mac_rxclk */
++ <1 RK_PB5 2 &pcfg_pull_none>,
++ /* mac_mdio */
++ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
++ /* mac_txen */
++ <1 RK_PD1 2 &pcfg_pull_none_4ma>,
++ /* mac_clk */
++ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
++ /* mac_rxdv */
++ <1 RK_PC6 2 &pcfg_pull_none>,
++ /* mac_mdc */
++ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
++ /* mac_rxd1 */
++ <1 RK_PB2 2 &pcfg_pull_none>,
++ /* mac_rxd0 */
++ <1 RK_PB3 2 &pcfg_pull_none>,
++ /* mac_txd1 */
++ <1 RK_PB0 2 &pcfg_pull_none_4ma>,
++ /* mac_txd0 */
++ <1 RK_PB1 2 &pcfg_pull_none_4ma>,
++ /* mac_rxd3 */
++ <1 RK_PB6 2 &pcfg_pull_none>,
++ /* mac_rxd2 */
++ <1 RK_PB7 2 &pcfg_pull_none>,
++ /* mac_txd3 */
++ <1 RK_PC0 2 &pcfg_pull_none_4ma>,
++ /* mac_txd2 */
++ <1 RK_PC1 2 &pcfg_pull_none_4ma>,
++
++ /* mac_txclk */
++ <0 RK_PB0 1 &pcfg_pull_none>,
++ /* mac_txen */
++ <0 RK_PB4 1 &pcfg_pull_none>,
++ /* mac_clk */
++ <0 RK_PD0 1 &pcfg_pull_none>,
++ /* mac_txd1 */
++ <0 RK_PC0 1 &pcfg_pull_none>,
++ /* mac_txd0 */
++ <0 RK_PC1 1 &pcfg_pull_none>,
++ /* mac_txd3 */
++ <0 RK_PC7 1 &pcfg_pull_none>,
++ /* mac_txd2 */
++ <0 RK_PC6 1 &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ host_vbus_drv: host-vbus-drv {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ otg_vbus_drv: otg-vbus-drv {
++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ gpio-leds {
++ leds_gpio: leds-gpio {
++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ max-frequency = <150000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
++ vmmc-supply = <&vcc_sd>;
++ status = "okay";
++};
++
++&sdmmc_ext {
++ bus-width = <4>;
++ cap-sd-highspeed;
++ cap-sdio-irq;
++ disable-wp;
++ keep-power-in-suspend;
++ max-frequency = <100000000>;
++ mmc-pwrseq = <&sdio_pwrseq>;
++ non-removable;
++ num-slots = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
++ rockchip,default-sample-phase = <120>;
++ supports-sdio;
++ sd-uhs-sdr104;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ brcmf: bcrmf@1 {
++ reg = <1>;
++ compatible = "brcm,bcm4329-fmac";
++ interrupt-parent = <&gpio1>;
++ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "host-wake";
++ };
++};
++
++&tsadc {
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&u2phy {
++ status = "okay";
++
++ u2phy_host: host-port {
++ status = "okay";
++ };
++
++ u2phy_otg: otg-port {
++ status = "okay";
++ };
++};
++
++&u3phy {
++ vbus-supply = <&vcc_host_vbus>;
++ status = "okay";
++};
++
++&u3phy_utmi {
++ status = "okay";
++};
++
++&u3phy_pipe {
++ status = "okay";
++};
++
++&usb20_otg {
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
++
++&usbdrd3 {
++ status = "okay";
++};
++
++&usbdrd_dwc3 {
++ status = "okay";
++};
diff --git
a/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328-nanopi-r2-rev00_dts
b/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328-nanopi-r2-rev00_dts
new file mode 100644
index 00000000000..a47c9b3002c
--- /dev/null
+++
b/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328-nanopi-r2-rev00_dts
@@ -0,0 +1,151 @@
+$OpenBSD$
+
+Index: arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts
+--- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts.orig
++++ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts
+@@ -0,0 +1,145 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ */
++
++/dts-v1/;
++#include <dt-bindings/input/linux-event-codes.h>
++#include "rk3328-nanopi-r2-common.dtsi"
++
++/ {
++ model = "FriendlyElec NanoPi R2S";
++ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ autorepeat;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&gpio_key1>;
++
++ button@0 {
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
++ label = "reset";
++ linux,code = <BTN_1>;
++ linux,input-type = <1>;
++ gpio-key,wakeup = <1>;
++ debounce-interval = <100>;
++ };
++ };
++
++ vcc_rtl8153: vcc-rtl8153-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb30_en_drv>;
++ regulator-always-on;
++ regulator-name = "vcc_rtl8153";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ off-on-delay-us = <5000>;
++ enable-active-high;
++ };
++};
++
++&mach {
++ hwrev = <0>;
++ model = "NanoPi R2S";
++};
++
++&emmc {
++ status = "disabled";
++};
++
++&i2c0 {
++ status = "okay";
++};
++
++&leds {
++ status = "okay";
++
++ led@2 {
++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
++ label = "lan_led";
++ };
++
++ led@3 {
++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
++ label = "wan_led";
++ };
++};
++
++&leds_gpio {
++ rockchip,pins =
++ <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
++ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
++ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++};
++
++&pwm2 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-1 = <&pwm2_sleep_pin>;
++ status = "okay";
++};
++
++&rk805 {
++ interrupt-parent = <&gpio1>;
++ interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
++};
++
++&vccio_sd {
++ status = "okay";
++};
++
++&io_domains {
++ vccio3-supply = <&vccio_sd>;
++};
++
++&sdmmc {
++ vqmmc-supply = <&vccio_sd>;
++ max-frequency = <150000000>;
++ sd-uhs-sdr50;
++ sd-uhs-sdr104;
++ status = "okay";
++};
++
++&sdmmc_ext {
++ status = "disabled";
++};
++
++&sdio_pwrseq {
++ status = "disabled";
++};
++
++&pinctrl {
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ pwm {
++ pwm2_sleep_pin: pwm2-sleep-pin {
++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO
&pcfg_output_low>;
++ };
++ };
++
++ rockchip-key {
++ gpio_key1: gpio-key1 {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ otg_vbus_drv: otg-vbus-drv {
++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ usb30_en_drv: usb30-en-drv {
++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
diff --git
a/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328_dtsi
b/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328_dtsi
new file mode 100644
index 00000000000..0269d274c68
--- /dev/null
+++ b/sysutils/dtb/patches/patch-arch_arm64_boot_dts_rockchip_rk3328_dtsi
@@ -0,0 +1,109 @@
+$OpenBSD$
+
+Index: arch/arm64/boot/dts/rockchip/rk3328.dtsi
+--- arch/arm64/boot/dts/rockchip/rk3328.dtsi.orig
++++ arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -793,7 +793,7 @@
+ <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
+- <&cru SCLK_RTC32K>;
++ <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
+ assigned-clock-parents =
+ <&cru HDMIPHY>, <&cru PLL_APLL>,
+ <&cru PLL_GPLL>, <&xin24m>,
+@@ -814,7 +814,7 @@
+ <150000000>, <75000000>,
+ <75000000>, <150000000>,
+ <75000000>, <75000000>,
+- <32768>;
++ <32768>, <32768>;
+ };
+
+ usb2phy_grf: syscon@ff450000 {
+@@ -854,6 +854,47 @@
+ };
+ };
+
++ usb3phy_grf: syscon@ff460000 {
++ compatible = "rockchip,usb3phy-grf", "syscon";
++ reg = <0x0 0xff460000 0x0 0x1000>;
++ };
++
++ u3phy: usb3-phy@ff470000 {
++ compatible = "rockchip,rk3328-u3phy";
++ reg = <0x0 0xff470000 0x0 0x0>;
++ rockchip,u3phygrf = <&usb3phy_grf>;
++ rockchip,grf = <&grf>;
++ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "linestate";
++ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
++ clock-names = "u3phy-otg", "u3phy-pipe";
++ resets = <&cru SRST_USB3PHY_U2>,
++ <&cru SRST_USB3PHY_U3>,
++ <&cru SRST_USB3PHY_PIPE>,
++ <&cru SRST_USB3OTG_UTMI>,
++ <&cru SRST_USB3PHY_OTG_P>,
++ <&cru SRST_USB3PHY_PIPE_P>;
++ reset-names = "u3phy-u2-por", "u3phy-u3-por",
++ "u3phy-pipe-mac", "u3phy-utmi-mac",
++ "u3phy-utmi-apb", "u3phy-pipe-apb";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++ status = "disabled";
++
++ u3phy_utmi: utmi@ff470000 {
++ reg = <0x0 0xff470000 0x0 0x8000>;
++ #phy-cells = <0>;
++ status = "disabled";
++ };
++
++ u3phy_pipe: pipe@ff478000 {
++ reg = <0x0 0xff478000 0x0 0x8000>;
++ #phy-cells = <0>;
++ status = "disabled";
++ };
++ };
++
+ sdmmc: mmc@ff500000 {
+ compatible = "rockchip,rk3328-dw-mshc",
"rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff500000 0x0 0x4000>;
+@@ -983,6 +1024,37 @@
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
++ };
++
++ usbdrd3: usb@ff600000 {
++ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
++ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
++ <&cru ACLK_USB3OTG>;
++ clock-names = "ref_clk", "suspend_clk",
++ "bus_clk";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++ status = "disabled";
++
++ usbdrd_dwc3: dwc3@ff600000 {
++ compatible = "snps,dwc3";
++ reg = <0x0 0xff600000 0x0 0x100000>;
++ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
++ dr_mode = "host";
++ phys = <&u3phy_utmi>, <&u3phy_pipe>;
++ phy-names = "usb2-phy", "usb3-phy";
++ phy_type = "utmi_wide";
++ snps,dis_enblslpm_quirk;
++ snps,dis-u2-freeclk-exists-quirk;
++ snps,dis_u2_susphy_quirk;
++ snps,dis-u3-autosuspend-quirk;
++ snps,dis_u3_susphy_quirk;
++ snps,dis-del-phy-power-chg-quirk;
++ snps,tx-ipgap-linecheck-dis-quirk;
++ snps,xhci-trb-ent-quirk;
++ status = "disabled";
++ };
+ };
+
+ gic: interrupt-controller@ff811000 {
