On Wed, Jun 03, 2020 at 08:31:08PM +0200, Patrick Wildt wrote:
> On Wed, Jun 03, 2020 at 08:15:44PM +0200, Patrick Wildt wrote:
> > On Wed, Jun 03, 2020 at 04:27:00PM +0100, Steve wrote:
> > > A pair of us have been using OpenBSB as our firewall for about 10
> > > years now, but the hardware is getting old and we want to replace
> > > it with a smaller / lower power device. With the new Arm boards out
> > > now we have been attempting to make a new version using the Nano Pi
> > > R2S from FriendlyElec which appears to be perfect, but we are not
> > > experienced in getting Arm SBC's working with OpenBSD.
> > >
> > > The R2S is an RK3328 based dual ethernet SBC and we have taken the
> > > rk3328-roc-cc.dts (Firefly board) as a base to modify, and compiled
> > > u-boot, with bl31 to get OpenBSD installed and running, as well as
> > > comparing the similar schematics.
> > >
> > > After OpenBSD boots, one of the ethernet ports which we believe to
> > > be connected directly to the RockChip is detected, giving a dwge0
> > > device, but the second ethernet port is not detected at all.
> > >
> > > From looking at the schematic diagram we think that the RTL8153 IC
> > > is connected via USB3.0 interface and we are not getting any USB3.0
> > > show up in the dmesg log.
> > >
> > > If were configured correctly, we think that we would expect to see a
> > > ure0 device. So this configuration needs to be added to the device
> > > tree.
> > >
> > > There is a working linux Armbian image which when checked allows
> > > access to both LAN ports. Converting their dtb->dts, there is a
> > > section for usb at 0xff6000000, which matches the RK3328 data sheet
> > > memory map for the USB3 register set.
> > >
> > > This, and the subsection dwc3, which we believe uses the phy's
> > > referenced as utmi and pipe, have many sections, such as the clocks,
> > > resets (and interrupts?) for which we can find no relevant information.
> > >
> > > Also of note is that on the schematic for the board, the pin GPIO2_C6
> > > seems to be required to be high to enable power to the USB subsystem,
> > > as VDD_5V_LAN powers the IO of the RTL8153 device.
> > >
> > > Further, the WAN-LED / LAN-LED from pins GPIO2_C2 / GPIO2_B7 remain
> > > off and unconfigured from the boot output even when we have attempted
> > > to direct them to be on.
> > >
> > > What are we are doing wrong in order to develop the dts to a working
> > > state? Any pointers to information on how to proceed and verify our
> > > progress would be appreciated. Especially, how do we set IO lines
> > > high so that we may power the USB3.0 subsystem and RTL8153 ?
> > >
> > >
> > > The defconfig is again based on the roc-cc one and contains:
> > >
> > > CONFIG_USB=y
> > > CONFIG_USB_XHCI_HCD=y
> > > CONFIG_USB_XHCI_DWC3=y
> > > CONFIG_USB_EHCI_HCD=y
> > > CONFIG_USB_EHCI_GENERIC=y
> > > CONFIG_USB_OHCI_HCD=y
> > > CONFIG_USB_OHCI_GENERIC=y
> > > CONFIG_USB_DWC2=y
> > > CONFIG_USB_DWC3=y
> > > # CONFIG_USB_DWC3_GADGET is not set
> > > CONFIG_USB_GADGET=y
> > > CONFIG_USB_GADGET_DWC2_OTG=y
> > >
> > > Also, relevant sections of our dts file are shown below.
> > >
> > > Many thanks.
> > >
> > > syscon: syscon@ff460000 {
> > > compatible = "rockchip,usb3phy-grf", "syscon";
> > > reg = <0x0 0xff460000 0x0 0x1000>;
> > > };
> > >
> > > u3phy: u3phy@ff470000 {
> > > compatible = "rockchip,rk3328-u3phy";
> > > reg = <0x0 0xff470000 0x0 0x0>;
> > > rockchip,u3phygrf = <&syscon>;
> > > rockchip,grf = <&grf>;
> > > interrupts = <0x0 0x4d 0x4>;
> > > interrupt-names = "linestate";
> > > clocks = <0x2 0xe0 0x2 0xe1>;
> > > clock-names = "u3phy-otg", "u3phy-pipe";
> > > resets = <0x2 0x7d 0x2 0x7e 0x2 0x7f 0x2 0x7c 0x2 0x9e 0x2 0x9f>;
> > > reset-names = "u3phy-u2-por", "u3phy-u3-por", "u3phy-pipe-mac",
> > > "u3phy-utmi-mac", "u3phy-utmi-apb", "u3phy-pipe-apb";
> > > #address-cells = <0x2>;
> > > #size-cells = <0x2>;
> > > ranges;
> > > status = "okay";
> > >
> > > utmi: utmi@ff470000 {
> > > reg = <0x0 0xff470000 0x0 0x8000>;
> > > #phy-cells = <0x0>;
> > > status = "okay";
> > > };
> > >
> > > pipe: pipe@ff478000 {
> > > reg = <0x0 0xff478000 0x0 0x8000>;
> > > #phy-cells = <0x0>;
> > > status = "okay";
> > > };
> > > };
> > >
> > > usb30: usb@ff600000 {
> > > compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
> > > clocks = <0x2 0x60 0x2 0x84 0x2 0x61>; // Should contain &u3phy?
> > > // Are some phandles?
> > > clock-names = "ref", "bus_early", "suspend";
> > > #address-cells = <0x2>;
> > > #size-cells = <0x2>;
> > > ranges;
> > > clock-ranges;
> > > status = "okay";
> > > phy-supply = <&vcc_usb30>;
> > >
> > > dwc3@ff600000 {
> > > compatible = "snps,dwc3";
> > > reg = <0x0 0xff600000 0x0 0x100000>;
> > > interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; // OK?
> > > dr_mode = "host";
> > > phys = <&utmi &pipe>;
> > > phy-names = "u2phy", "u3phy";
> > > phy_type = "utmi_wide";
> > > snps,dis_enblslpm_quirk;
> > > snps,dis-u2-freeclk-exists-quirk;
> > > snps,dis_u2_susphy_quirk;
> > > snps,dis_u3_susphy_quirk;
> > > snps,dis-del-phy-power-chg-quirk;
> > > snps,dis-tx-ipgap-linecheck-quirk;
> > > snps,xhci-trb-ent-quirk;
> > > status = "okay";
> > > #address-cells = <0x1>;
> > > #size-cells = <0x0>;
> > >
> > > device@2 {
> > > compatible = "usbbda:8153";
> > > reg = <0x2>;
> > > local-mac-address = [00 00 00 00 00 00];
> > > };
> > > };
> > > };
> > >
> > > vcc-sys {
> > > compatible = "regulator-fixed";
> > > regulator-name = "vcc_usb30";
> > > regulator-always-on;
> > > regulator-boot-on;
> > > gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&i2s1_sdio3>;
> > > regulator-min-microvolt = <5000000>;
> > > regulator-max-microvolt = <5000000>;
> > > vin-supply = <&vcc_io>;
> > > };
> > >
> > > leds_all: leds {
> > > compatible = "gpio-leds";
> > >
> > > status {
> > > label = "r2s:red:status";
> > > linux,default-trigger = "heartbeat";
> > > gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
> > > default-state = "on";
> > > };
> > >
> > > wan {
> > > label = "r2s:green:wan";
> > > gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
> > > default-state = "on";
> > > };
> > >
> > > lan {
> > > label = "r2s:green:lan";
> > > gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
> > > default-state = "on";
> > > };
> > > };
> > >
> > > &vcc_usb30 {
> > > status = "okay";
> > > };
> > >
> > > &leds_all {
> > > status = "okay";
> > > };
> > >
> >
> > About 6 weeks ago I build my own U-Boot for the R2S, based on what's in
> > U-Boot master, and also built a device tree based on Linux master, I
> > think, and also the patches in FriendlyARM's repo. Here's the DTB,
> > put this onto your MS-DOS partition and make sure that U-Boot loads
> > that file (and not something else).
> >
> > The u-boot environment contains an fdtfile or fdt_file variable. You
> > can either change that variable to reflect the filename, or you can
> > put the file onto the MS-DOS partition with the name as in the variable.
> >
> > Patrick
>
> This is the diff I had in sysutils/dtb, but that was based on the 5.6
> port and the port is now using 5.7.
And here's a bit of the diff I had for sysutils/u-boot, but I'm not sure
it builds right now.
diff --git a/sysutils/u-boot/patches/patch-arch_arm_dts_Makefile
b/sysutils/u-boot/patches/patch-arch_arm_dts_Makefile
new file mode 100644
index 00000000000..dd9813afb31
--- /dev/null
+++ b/sysutils/u-boot/patches/patch-arch_arm_dts_Makefile
@@ -0,0 +1,13 @@
+$OpenBSD$
+
+Index: arch/arm/dts/Makefile
+--- arch/arm/dts/Makefile.orig
++++ arch/arm/dts/Makefile
+@@ -104,6 +104,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+
+ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ rk3328-evb.dtb \
++ rk3328-nanopi-r2s.dtb \
+ rk3328-rock64.dtb
+
+ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
diff --git
a/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2-common_dtsi
b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2-common_dtsi
new file mode 100644
index 00000000000..6fd671cbc3e
--- /dev/null
+++ b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2-common_dtsi
@@ -0,0 +1,324 @@
+$OpenBSD$
+
+Index: arch/arm/dts/rk3328-nanopi-r2-common.dtsi
+--- arch/arm/dts/rk3328-nanopi-r2-common.dtsi.orig
++++ arch/arm/dts/rk3328-nanopi-r2-common.dtsi
+@@ -0,0 +1,318 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
++ */
++
++/dts-v1/;
++//#include "rk3328-dram-default-timing.dtsi"
++#include "rk3328.dtsi"
++
++/ {
++ model = "FriendlyElec boards based on Rockchip RK3328";
++ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ gmac_clkin: external-gmac-clock {
++ compatible = "fixed-clock";
++ clock-frequency = <125000000>;
++ clock-output-names = "gmac_clkin";
++ #clock-cells = <0>;
++ };
++
++ vcc_sd: sdmmc-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0m1_gpio>;
++ regulator-name = "vcc_sd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vccio_sd>;
++ };
++
++ vccio_sd: sdmmcio-regulator {
++ compatible = "regulator-fixed";
++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_LOW>;
++ regulator-name = "vccio_sd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_io>;
++ startup-delay-us = <2000>;
++ regulator-settling-time-us = <5000>;
++ };
++
++ vcc_host_vbus: host-vbus-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_host_vbus";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc_sys: vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc_phy: vcc-phy-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_phy";
++ regulator-always-on;
++ regulator-boot-on;
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&emmc {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ max-frequency = <150000000>;
++ mmc-hs200-1_8v;
++ no-sd;
++ non-removable;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
++ vmmc-supply = <&vcc_io>;
++ vqmmc-supply = <&vcc18_emmc>;
++ status = "okay";
++};
++
++&gmac2io {
++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
++ clock_in_out = "input";
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmiim1_pins>;
++ phy-handle = <&rtl8211e>;
++ phy-mode = "rgmii";
++ phy-supply = <&vcc_phy>;
++ snps,reset-active-low;
++ snps,reset-delays-us = <0 10000 30000>;
++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ snps,aal;
++ snps,rxpbl = <0x4>;
++ snps,txpbl = <0x4>;
++ tx_delay = <0x24>;
++ rx_delay = <0x18>;
++ status = "okay";
++
++ mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtl8211e: phy@0 {
++ reg = <0>;
++ reset-assert-us = <10000>;
++ reset-deassert-us = <30000>;
++ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
++ };
++ };
++};
++
++&i2c1 {
++ status = "okay";
++
++ rk805: rk805@18 {
++ compatible = "rockchip,rk805";
++ reg = <0x18>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ clock-output-names = "xin32k", "rk805-clkout2";
++ gpio-controller;
++ #gpio-cells = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int_l>;
++ rockchip,system-power-controller;
++ wakeup-source;
++
++ vcc1-supply = <&vcc_sys>;
++ vcc2-supply = <&vcc_sys>;
++ vcc3-supply = <&vcc_sys>;
++ vcc4-supply = <&vcc_sys>;
++ vcc5-supply = <&vcc_io>;
++ vcc6-supply = <&vcc_io>;
++
++ regulators {
++ vdd_logic: DCDC_REG1 {
++ regulator-name = "vdd_logic";
++ regulator-init-microvolt = <1075000>;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++
++ vdd_arm: DCDC_REG2 {
++ regulator-name = "vdd_arm";
++ regulator-init-microvolt = <1225000>;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <950000>;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_io: DCDC_REG4 {
++ regulator-name = "vcc_io";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc_18: LDO_REG1 {
++ regulator-name = "vcc_18";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc18_emmc: LDO_REG2 {
++ regulator-name = "vcc18_emmc";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_10: LDO_REG3 {
++ regulator-name = "vdd_10";
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++ };
++ };
++};
++
++&io_domains {
++ status = "okay";
++
++ vccio1-supply = <&vcc_io>;
++ vccio2-supply = <&vcc18_emmc>;
++ vccio3-supply = <&vcc_io>;
++ vccio4-supply = <&vcc_io>;
++ vccio5-supply = <&vcc_io>;
++ vccio6-supply = <&vcc_18>;
++ pmuio-supply = <&vcc_io>;
++};
++
++&pinctrl {
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ usb {
++ host_vbus_drv: host-vbus-drv {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ otg_vbus_drv: otg-vbus-drv {
++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ max-frequency = <150000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
++ vmmc-supply = <&vcc_sd>;
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&u2phy {
++ status = "okay";
++
++ u2phy_host: host-port {
++ status = "okay";
++ };
++
++ u2phy_otg: otg-port {
++ status = "okay";
++ };
++};
++
++&usb20_otg {
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
diff --git
a/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2s-u-boot_dtsi
b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2s-u-boot_dtsi
new file mode 100644
index 00000000000..f8ee81c2f97
--- /dev/null
+++ b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2s-u-boot_dtsi
@@ -0,0 +1,43 @@
+$OpenBSD$
+
+Index: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+--- arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi.orig
++++ arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+@@ -0,0 +1,37 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
++ */
++
++#include "rk3328-u-boot.dtsi"
++#include "rk3328-sdram-ddr4-666.dtsi"
++/ {
++ chosen {
++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
++ };
++};
++
++&gpio0 {
++ u-boot,dm-spl;
++};
++
++&pinctrl {
++ u-boot,dm-spl;
++};
++
++&sdmmc0m1_gpio {
++ u-boot,dm-spl;
++};
++
++&pcfg_pull_up_4ma {
++ u-boot,dm-spl;
++};
++
++&usb_host0_xhci {
++ status = "okay";
++};
++
++/* Need this and all the pinctrl/gpio stuff above to set pinmux */
++&vcc_sd {
++ u-boot,dm-spl;
++};
diff --git a/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2s_dts
b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2s_dts
new file mode 100644
index 00000000000..e9ccb75a575
--- /dev/null
+++ b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-nanopi-r2s_dts
@@ -0,0 +1,103 @@
+$OpenBSD$
+
+Index: arch/arm/dts/rk3328-nanopi-r2s.dts
+--- arch/arm/dts/rk3328-nanopi-r2s.dts.orig
++++ arch/arm/dts/rk3328-nanopi-r2s.dts
+@@ -0,0 +1,97 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ */
++
++/dts-v1/;
++#include <dt-bindings/input/linux-event-codes.h>
++#include "rk3328-nanopi-r2-common.dtsi"
++
++/ {
++ model = "FriendlyElec NanoPi R2S";
++ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ autorepeat;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&gpio_key1>;
++
++ button@0 {
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
++ label = "reset";
++ linux,code = <BTN_1>;
++ linux,input-type = <1>;
++ gpio-key,wakeup = <1>;
++ debounce-interval = <100>;
++ };
++ };
++
++ vcc_rtl8153: vcc-rtl8153-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb30_en_drv>;
++ regulator-always-on;
++ regulator-name = "vcc_rtl8153";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ off-on-delay-us = <5000>;
++ enable-active-high;
++ };
++};
++
++&emmc {
++ status = "disabled";
++};
++
++&i2c0 {
++ status = "okay";
++};
++
++&rk805 {
++ interrupt-parent = <&gpio1>;
++ interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
++};
++
++&sdmmc {
++// vqmmc-supply = <&vccio_sd>;
++ max-frequency = <150000000>;
++// sd-uhs-sdr50;
++// sd-uhs-sdr104;
++ status = "okay";
++};
++
++&pinctrl {
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ pwm {
++ pwm2_sleep_pin: pwm2-sleep-pin {
++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO
&pcfg_output_low>;
++ };
++ };
++
++ rockchip-key {
++ gpio_key1: gpio-key1 {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ otg_vbus_drv: otg-vbus-drv {
++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ usb30_en_drv: usb30-en-drv {
++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
diff --git a/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-rock64_dts
b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-rock64_dts
index fd45383e869..0da9960b494 100644
--- a/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-rock64_dts
+++ b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328-rock64_dts
@@ -3,12 +3,219 @@ $OpenBSD: patch-arch_arm_dts_rk3328-rock64_dts,v 1.1
2019/10/08 01:10:28 kurt Ex
Index: arch/arm/dts/rk3328-rock64.dts
--- arch/arm/dts/rk3328-rock64.dts.orig
+++ arch/arm/dts/rk3328-rock64.dts
-@@ -11,7 +11,7 @@
- compatible = "pine64,rock64", "rockchip,rk3328";
+@@ -43,6 +43,17 @@
+ vin-supply = <&vcc_sys>;
+ };
+
++ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb20_host_drv>;
++ regulator-name = "vcc_host1_5v";
++ regulator-always-on;
++ regulator-boot-on;
++ vin-supply = <&vcc_sys>;
++ };
++
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+@@ -51,8 +62,58 @@
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
++
++ ir-receiver {
++ compatible = "gpio-ir-receiver";
++ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
++ pinctrl-0 = <&ir_int>;
++ pinctrl-names = "default";
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ power {
++ gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "mmc0";
++ };
++
++ standby {
++ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ sound {
++ compatible = "audio-graph-card";
++ label = "rockchip,rk3328";
++ dais = <&i2s1_p0
++ &spdif_p0>;
++ };
++
++ spdif-dit {
++ compatible = "linux,spdif-dit";
++ #sound-dai-cells = <0>;
++
++ port {
++ dit_p0_0: endpoint {
++ remote-endpoint = <&spdif_p0_0>;
++ };
++ };
++ };
+ };
+
++&codec {
++ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
++ status = "okay";
++
++ port@0 {
++ codec_p0_0: endpoint {
++ remote-endpoint = <&i2s1_p0_0>;
++ };
++ };
++};
++
+ &cpu0 {
+ cpu-supply = <&vdd_arm>;
+ };
+@@ -98,16 +159,26 @@
+ status = "okay";
+ };
- chosen {
-- stdout-path = "serial2:1500000n8";
-+ stdout-path = "serial2:115200n8";
++&hdmi {
++ status = "okay";
++};
++
++&hdmiphy {
++ status = "okay";
++};
++
+ &i2c1 {
+ status = "okay";
+
+- rk805: rk805@18 {
++ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
++ gpio-controller;
++ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+@@ -169,7 +240,7 @@
+ };
+
+ vcc_18: LDO_REG1 {
+- regulator-name = "vdd_18";
++ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+@@ -181,7 +252,7 @@
+ };
+
+ vcc18_emmc: LDO_REG2 {
+- regulator-name = "vcc_18emmc";
++ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+@@ -207,6 +278,18 @@
};
+ };
+
++&i2s1 {
++ status = "okay";
++
++ i2s1_p0: port {
++ i2s1_p0_0: endpoint {
++ dai-format = "i2s";
++ mclk-fs = <256>;
++ remote-endpoint = <&codec_p0_0>;
++ };
++ };
++};
++
+ &io_domains {
+ status = "okay";
+
+@@ -220,6 +303,12 @@
+ };
+
+ &pinctrl {
++ ir {
++ ir_int: ir-int {
++ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+@@ -245,6 +334,17 @@
+ status = "okay";
+ };
+
++&spdif {
++ pinctrl-0 = <&spdifm0_tx>;
++ status = "okay";
++
++ spdif_p0: port {
++ spdif_p0_0: endpoint {
++ remote-endpoint = <&dit_p0_0>;
++ };
++ };
++};
++
+ &spi0 {
+ status = "okay";
+
+@@ -257,10 +357,28 @@
+ };
+ };
+
++&tsadc {
++ rockchip,hw-tshut-mode = <0>;
++ rockchip,hw-tshut-polarity = <0>;
++ status = "okay";
++};
++
+ &uart2 {
+ status = "okay";
+ };
+
++&u2phy {
++ status = "okay";
++
++ u2phy_host: host-port {
++ status = "okay";
++ };
++
++ u2phy_otg: otg-port {
++ status = "okay";
++ };
++};
++
+ &usb20_otg {
+ dr_mode = "host";
+ status = "okay";
+@@ -271,5 +389,13 @@
+ };
- gmac_clkin: external-gmac-clock {
+ &usb_host0_ohci {
++ status = "okay";
++};
++
++&vop {
++ status = "okay";
++};
++
++&vop_mmu {
+ status = "okay";
+ };
diff --git a/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328_dtsi
b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328_dtsi
new file mode 100644
index 00000000000..542d6f73437
--- /dev/null
+++ b/sysutils/u-boot/patches/patch-arch_arm_dts_rk3328_dtsi
@@ -0,0 +1,2178 @@
+$OpenBSD$
+
+Index: arch/arm/dts/rk3328.dtsi
+--- arch/arm/dts/rk3328.dtsi.orig
++++ arch/arm/dts/rk3328.dtsi
+@@ -1,6 +1,6 @@
+-// SPDX-License-Identifier: GPL-2.0+
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+ #include <dt-bindings/clock/rk3328-cru.h>
+@@ -8,6 +8,9 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/power/rk3328-power.h>
++#include <dt-bindings/soc/rockchip,boot-mode.h>
++#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ compatible = "rockchip,rk3328";
+@@ -24,9 +27,8 @@
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+- mmc0 = &emmc;
+- mmc1 = &sdmmc;
+- mmc2 = &sdmmc_ext;
++ ethernet0 = &gmac2io;
++ ethernet1 = &gmac2phy;
+ };
+
+ cpus {
+@@ -35,69 +37,144 @@
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+- compatible = "arm,cortex-a53", "arm,armv8";
++ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
++ clocks = <&cru ARMCLK>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ dynamic-power-coefficient = <120>;
+ enable-method = "psci";
+-// clocks = <&cru ARMCLK>;
++ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
++
+ cpu1: cpu@1 {
+ device_type = "cpu";
+- compatible = "arm,cortex-a53", "arm,armv8";
++ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
++ clocks = <&cru ARMCLK>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ dynamic-power-coefficient = <120>;
+ enable-method = "psci";
++ next-level-cache = <&l2>;
++ operating-points-v2 = <&cpu0_opp_table>;
+ };
++
+ cpu2: cpu@2 {
+ device_type = "cpu";
+- compatible = "arm,cortex-a53", "arm,armv8";
++ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
++ clocks = <&cru ARMCLK>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ dynamic-power-coefficient = <120>;
+ enable-method = "psci";
++ next-level-cache = <&l2>;
++ operating-points-v2 = <&cpu0_opp_table>;
+ };
++
+ cpu3: cpu@3 {
+ device_type = "cpu";
+- compatible = "arm,cortex-a53", "arm,armv8";
++ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
++ clocks = <&cru ARMCLK>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ dynamic-power-coefficient = <120>;
+ enable-method = "psci";
++ next-level-cache = <&l2>;
++ operating-points-v2 = <&cpu0_opp_table>;
+ };
++
++ idle-states {
++ entry-method = "psci";
++
++ CPU_SLEEP: cpu-sleep {
++ compatible = "arm,idle-state";
++ local-timer-stop;
++ arm,psci-suspend-param = <0x0010000>;
++ entry-latency-us = <120>;
++ exit-latency-us = <250>;
++ min-residency-us = <900>;
++ };
++ };
++
++ l2: l2-cache0 {
++ compatible = "cache";
++ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+- opp@408000000 {
++ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+- opp@600000000 {
++ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ };
+- opp@816000000 {
++ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <40000>;
+ };
+- opp@1008000000 {
++ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+- opp@1200000000 {
++ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1225000>;
+ clock-latency-ns = <40000>;
+ };
+- opp@1296000000 {
++ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1300000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
++ amba: bus {
++ compatible = "simple-bus";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ dmac: dmac@ff1f0000 {
++ compatible = "arm,pl330", "arm,primecell";
++ reg = <0x0 0xff1f0000 0x0 0x4000>;
++ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru ACLK_DMAC>;
++ clock-names = "apb_pclk";
++ #dma-cells = <1>;
++ };
++ };
++
++ analog_sound: analog-sound {
++ compatible = "simple-audio-card";
++ simple-audio-card,format = "i2s";
++ simple-audio-card,mclk-fs = <256>;
++ simple-audio-card,name = "Analog";
++ status = "disabled";
++
++ simple-audio-card,cpu {
++ sound-dai = <&i2s1>;
++ };
++
++ simple-audio-card,codec {
++ sound-dai = <&codec>;
++ };
++ };
++
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+@@ -107,8 +184,29 @@
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
++ display_subsystem: display-subsystem {
++ compatible = "rockchip,display-subsystem";
++ ports = <&vop_out>;
++ };
++
++ hdmi_sound: hdmi-sound {
++ compatible = "simple-audio-card";
++ simple-audio-card,format = "i2s";
++ simple-audio-card,mclk-fs = <128>;
++ simple-audio-card,name = "HDMI";
++ status = "disabled";
++
++ simple-audio-card,cpu {
++ sound-dai = <&i2s0>;
++ };
++
++ simple-audio-card,codec {
++ sound-dai = <&hdmi>;
++ };
++ };
++
+ psci {
+- compatible = "arm,psci-1.0";
++ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+@@ -134,8 +232,8 @@
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 11>, <&dmac 12>;
+- #dma-cells = <2>;
+ dma-names = "tx", "rx";
++ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+@@ -146,8 +244,8 @@
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 14>, <&dmac 15>;
+- #dma-cells = <2>;
+ dma-names = "tx", "rx";
++ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+@@ -158,16 +256,8 @@
+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 0>, <&dmac 1>;
+- #dma-cells = <2>;
+ dma-names = "tx", "rx";
+- pinctrl-names = "default", "sleep";
+- pinctrl-0 = <&i2s2m0_mclk
+- &i2s2m0_sclk
+- &i2s2m0_lrcktx
+- &i2s2m0_lrckrx
+- &i2s2m0_sdo
+- &i2s2m0_sdi>;
+- pinctrl-1 = <&i2s2m0_sleep>;
++ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+@@ -178,13 +268,34 @@
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 10>;
+- #dma-cells = <1>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm2_tx>;
++ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
++ pdm: pdm@ff040000 {
++ compatible = "rockchip,pdm";
++ reg = <0x0 0xff040000 0x0 0x1000>;
++ clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
++ clock-names = "pdm_clk", "pdm_hclk";
++ dmas = <&dmac 16>;
++ dma-names = "rx";
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&pdmm0_clk
++ &pdmm0_sdi0
++ &pdmm0_sdi1
++ &pdmm0_sdi2
++ &pdmm0_sdi3>;
++ pinctrl-1 = <&pdmm0_clk_sleep
++ &pdmm0_sdi0_sleep
++ &pdmm0_sdi1_sleep
++ &pdmm0_sdi2_sleep
++ &pdmm0_sdi3_sleep>;
++ status = "disabled";
++ };
++
+ grf: syscon@ff100000 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff100000 0x0 0x1000>;
+@@ -193,6 +304,39 @@
+ compatible = "rockchip,rk3328-io-voltage-domain";
+ status = "disabled";
+ };
++
++ grf_gpio: grf-gpio {
++ compatible = "rockchip,rk3328-grf-gpio";
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ power: power-controller {
++ compatible = "rockchip,rk3328-power-controller";
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ pd_hevc@RK3328_PD_HEVC {
++ reg = <RK3328_PD_HEVC>;
++ };
++ pd_video@RK3328_PD_VIDEO {
++ reg = <RK3328_PD_VIDEO>;
++ };
++ pd_vpu@RK3328_PD_VPU {
++ reg = <RK3328_PD_VPU>;
++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++ };
++ };
++
++ reboot-mode {
++ compatible = "syscon-reboot-mode";
++ offset = <0x5c8>;
++ mode-normal = <BOOT_NORMAL>;
++ mode-recovery = <BOOT_RECOVERY>;
++ mode-bootloader = <BOOT_FASTBOOT>;
++ mode-loader = <BOOT_BL_DOWNLOAD>;
++ };
+ };
+
+ uart0: serial@ff110000 {
+@@ -201,12 +345,12 @@
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+- reg-shift = <2>;
+- reg-io-width = <4>;
+ dmas = <&dmac 2>, <&dmac 3>;
+- #dma-cells = <2>;
++ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
+ status = "disabled";
+ };
+
+@@ -215,13 +359,13 @@
+ reg = <0x0 0xff120000 0x0 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+- clock-names = "sclk_uart", "pclk_uart";
+- reg-shift = <2>;
+- reg-io-width = <4>;
++ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 4>, <&dmac 5>;
+- #dma-cells = <2>;
++ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
+ status = "disabled";
+ };
+
+@@ -231,22 +375,17 @@
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+- reg-shift = <2>;
+- reg-io-width = <4>;
+ dmas = <&dmac 6>, <&dmac 7>;
+- #dma-cells = <2>;
++ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
+ status = "disabled";
+ };
+
+- pmu: power-management@ff140000 {
+- compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
+- reg = <0x0 0xff140000 0x0 0x1000>;
+- };
+-
+ i2c0: i2c@ff150000 {
+- compatible = "rockchip,rk3328-i2c";
++ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff150000 0x0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+@@ -259,7 +398,7 @@
+ };
+
+ i2c1: i2c@ff160000 {
+- compatible = "rockchip,rk3328-i2c";
++ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+@@ -272,7 +411,7 @@
+ };
+
+ i2c2: i2c@ff170000 {
+- compatible = "rockchip,rk3328-i2c";
++ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff170000 0x0 0x1000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+@@ -285,7 +424,7 @@
+ };
+
+ i2c3: i2c@ff180000 {
+- compatible = "rockchip,rk3328-i2c";
++ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff180000 0x0 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+@@ -306,7 +445,6 @@
+ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 8>, <&dmac 9>;
+- #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
+@@ -317,28 +455,141 @@
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0xff1a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru PCLK_WDT>;
++ };
++
++ pwm0: pwm@ff1b0000 {
++ compatible = "rockchip,rk3328-pwm";
++ reg = <0x0 0xff1b0000 0x0 0x10>;
++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
++ clock-names = "pwm", "pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm0_pin>;
++ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+- amba {
+- compatible = "simple-bus";
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges;
++ pwm1: pwm@ff1b0010 {
++ compatible = "rockchip,rk3328-pwm";
++ reg = <0x0 0xff1b0010 0x0 0x10>;
++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
++ clock-names = "pwm", "pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm1_pin>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- dmac: dmac@ff1f0000 {
+- compatible = "arm,pl330", "arm,primecell";
+- reg = <0x0 0xff1f0000 0x0 0x4000>;
+- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&cru ACLK_DMAC>;
+- clock-names = "apb_pclk";
+- #dma-cells = <1>;
++ pwm2: pwm@ff1b0020 {
++ compatible = "rockchip,rk3328-pwm";
++ reg = <0x0 0xff1b0020 0x0 0x10>;
++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
++ clock-names = "pwm", "pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm2_pin>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ pwm3: pwm@ff1b0030 {
++ compatible = "rockchip,rk3328-pwm";
++ reg = <0x0 0xff1b0030 0x0 0x10>;
++ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
++ clock-names = "pwm", "pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwmir_pin>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ thermal-zones {
++ soc_thermal: soc-thermal {
++ polling-delay-passive = <20>;
++ polling-delay = <1000>;
++ sustainable-power = <1000>;
++
++ thermal-sensors = <&tsadc 0>;
++
++ trips {
++ threshold: trip-point0 {
++ temperature = <70000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ target: trip-point1 {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ soc_crit: soc-crit {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&target>;
++ cooling-device = <&cpu0
THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu1
THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu2
THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu3
THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ contribution = <4096>;
++ };
++ };
+ };
++
+ };
+
+- saradc: saradc@ff280000 {
+- compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
++ tsadc: tsadc@ff250000 {
++ compatible = "rockchip,rk3328-tsadc";
++ reg = <0x0 0xff250000 0x0 0x100>;
++ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++ assigned-clocks = <&cru SCLK_TSADC>;
++ assigned-clock-rates = <50000>;
++ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
++ clock-names = "tsadc", "apb_pclk";
++ pinctrl-names = "init", "default", "sleep";
++ pinctrl-0 = <&otp_gpio>;
++ pinctrl-1 = <&otp_out>;
++ pinctrl-2 = <&otp_gpio>;
++ resets = <&cru SRST_TSADC>;
++ reset-names = "tsadc-apb";
++ rockchip,grf = <&grf>;
++ rockchip,hw-tshut-temp = <100000>;
++ #thermal-sensor-cells = <1>;
++ status = "disabled";
++ };
++
++ efuse: efuse@ff260000 {
++ compatible = "rockchip,rk3328-efuse";
++ reg = <0x0 0xff260000 0x0 0x50>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ clocks = <&cru SCLK_EFUSE>;
++ clock-names = "pclk_efuse";
++ rockchip,efuse-size = <0x20>;
++
++ /* Data cells */
++ efuse_id: id@7 {
++ reg = <0x07 0x10>;
++ };
++ cpu_leakage: cpu-leakage@17 {
++ reg = <0x17 0x1>;
++ };
++ logic_leakage: logic-leakage@19 {
++ reg = <0x19 0x1>;
++ };
++ efuse_cpu_version: cpu-version@1a {
++ reg = <0x1a 0x1>;
++ bits = <3 3>;
++ };
++ };
++
++ saradc: adc@ff280000 {
++ compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
+ reg = <0x0 0xff280000 0x0 0x100>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+@@ -349,6 +600,169 @@
+ status = "disabled";
+ };
+
++ gpu: gpu@ff300000 {
++ compatible = "rockchip,rk3328-mali", "arm,mali-450";
++ reg = <0x0 0xff300000 0x0 0x40000>;
++ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "gp",
++ "gpmmu",
++ "pp",
++ "pp0",
++ "ppmmu0",
++ "pp1",
++ "ppmmu1";
++ clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
++ clock-names = "bus", "core";
++ resets = <&cru SRST_GPU_A>;
++ };
++
++ h265e_mmu: iommu@ff330200 {
++ compatible = "rockchip,iommu";
++ reg = <0x0 0xff330200 0 0x100>;
++ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "h265e_mmu";
++ clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
++ clock-names = "aclk", "iface";
++ #iommu-cells = <0>;
++ status = "disabled";
++ };
++
++ vepu_mmu: iommu@ff340800 {
++ compatible = "rockchip,iommu";
++ reg = <0x0 0xff340800 0x0 0x40>;
++ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "vepu_mmu";
++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++ clock-names = "aclk", "iface";
++ #iommu-cells = <0>;
++ status = "disabled";
++ };
++
++ vpu: video-codec@ff350000 {
++ compatible = "rockchip,rk3328-vpu";
++ reg = <0x0 0xff350000 0x0 0x800>;
++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "vdpu";
++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++ clock-names = "aclk", "hclk";
++ iommus = <&vpu_mmu>;
++ power-domains = <&power RK3328_PD_VPU>;
++ };
++
++ vpu_mmu: iommu@ff350800 {
++ compatible = "rockchip,iommu";
++ reg = <0x0 0xff350800 0x0 0x40>;
++ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "vpu_mmu";
++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++ clock-names = "aclk", "iface";
++ #iommu-cells = <0>;
++ power-domains = <&power RK3328_PD_VPU>;
++ };
++
++ rkvdec_mmu: iommu@ff360480 {
++ compatible = "rockchip,iommu";
++ reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
++ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "rkvdec_mmu";
++ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
++ clock-names = "aclk", "iface";
++ #iommu-cells = <0>;
++ status = "disabled";
++ };
++
++ vop: vop@ff370000 {
++ compatible = "rockchip,rk3328-vop";
++ reg = <0x0 0xff370000 0x0 0x3efc>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
++ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
++ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru
SRST_VOP_D>;
++ reset-names = "axi", "ahb", "dclk";
++ iommus = <&vop_mmu>;
++ status = "disabled";
++
++ vop_out: port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ vop_out_hdmi: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&hdmi_in_vop>;
++ };
++ };
++ };
++
++ vop_mmu: iommu@ff373f00 {
++ compatible = "rockchip,iommu";
++ reg = <0x0 0xff373f00 0x0 0x100>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "vop_mmu";
++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
++ clock-names = "aclk", "iface";
++ #iommu-cells = <0>;
++ status = "disabled";
++ };
++
++ hdmi: hdmi@ff3c0000 {
++ compatible = "rockchip,rk3328-dw-hdmi";
++ reg = <0x0 0xff3c0000 0x0 0x20000>;
++ reg-io-width = <4>;
++ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru PCLK_HDMI>,
++ <&cru SCLK_HDMI_SFC>,
++ <&cru SCLK_RTC32K>;
++ clock-names = "iahb",
++ "isfr",
++ "cec";
++ phys = <&hdmiphy>;
++ phy-names = "hdmi";
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
++ rockchip,grf = <&grf>;
++ #sound-dai-cells = <0>;
++ status = "disabled";
++
++ ports {
++ hdmi_in: port {
++ hdmi_in_vop: endpoint {
++ remote-endpoint = <&vop_out_hdmi>;
++ };
++ };
++ };
++ };
++
++ codec: codec@ff410000 {
++ compatible = "rockchip,rk3328-codec";
++ reg = <0x0 0xff410000 0x0 0x1000>;
++ clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
++ clock-names = "pclk", "mclk";
++ rockchip,grf = <&grf>;
++ #sound-dai-cells = <0>;
++ status = "disabled";
++ };
++
++ hdmiphy: phy@ff430000 {
++ compatible = "rockchip,rk3328-hdmi-phy";
++ reg = <0x0 0xff430000 0x0 0x10000>;
++ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
++ clock-names = "sysclk", "refoclk", "refpclk";
++ clock-output-names = "hdmi_phy";
++ #clock-cells = <0>;
++ nvmem-cells = <&efuse_cpu_version>;
++ nvmem-cell-names = "cpu-version";
++ #phy-cells = <0>;
++ status = "disabled";
++ };
++
+ cru: clock-controller@ff440000 {
+ compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
+ reg = <0x0 0xff440000 0x0 0x1000>;
+@@ -356,6 +770,12 @@
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks =
++ /*
++ * CPLL should run at 1200, but that is to high for
++ * the initial dividers of most of its children.
++ * We need set cpll child clk div first,
++ * and then set the cpll frequency.
++ */
+ <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
+ <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
+ <&cru SCLK_UART1>, <&cru SCLK_UART2>,
+@@ -371,15 +791,7 @@
+ <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
+- <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
+- <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
+- <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
+- <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
+- <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
+- <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
+- <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
+- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
+- <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
++ <&cru SCLK_RTC32K>;
+ assigned-clock-parents =
+ <&cru HDMIPHY>, <&cru PLL_APLL>,
+ <&cru PLL_GPLL>, <&xin24m>,
+@@ -400,55 +812,85 @@
+ <150000000>, <75000000>,
+ <75000000>, <150000000>,
+ <75000000>, <75000000>,
+- <300000000>, <100000000>,
+- <300000000>, <200000000>,
+- <400000000>, <500000000>,
+- <200000000>, <300000000>,
+- <300000000>, <250000000>,
+- <200000000>, <100000000>,
+- <24000000>, <100000000>,
+- <150000000>, <50000000>,
+- <32768>, <32768>;
++ <32768>;
+ };
+
+- sdmmc: rksdmmc@ff500000 {
++ usb2phy_grf: syscon@ff450000 {
++ compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
++ "simple-mfd";
++ reg = <0x0 0xff450000 0x0 0x10000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ u2phy: usb2-phy@100 {
++ compatible = "rockchip,rk3328-usb2phy";
++ reg = <0x100 0x10>;
++ clocks = <&xin24m>;
++ clock-names = "phyclk";
++ clock-output-names = "usb480m_phy";
++ #clock-cells = <0>;
++ assigned-clocks = <&cru USB480M>;
++ assigned-clock-parents = <&u2phy>;
++ status = "disabled";
++
++ u2phy_otg: otg-port {
++ #phy-cells = <0>;
++ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "otg-bvalid", "otg-id",
++ "linestate";
++ status = "disabled";
++ };
++
++ u2phy_host: host-port {
++ #phy-cells = <0>;
++ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "linestate";
++ status = "disabled";
++ };
++ };
++ };
++
++ sdmmc: mmc@ff500000 {
+ compatible = "rockchip,rk3328-dw-mshc",
"rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff500000 0x0 0x4000>;
+- max-frequency = <150000000>;
+- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+- clock-names = "biu", "ciu";
+- fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
++ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++ fifo-depth = <0x100>;
++ max-frequency = <150000000>;
+ status = "disabled";
+ };
+
+- sdio: dwmmc@ff510000 {
++ sdio: mmc@ff510000 {
+ compatible = "rockchip,rk3328-dw-mshc",
"rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff510000 0x0 0x4000>;
+- max-frequency = <150000000>;
++ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
++ max-frequency = <150000000>;
+ status = "disabled";
+ };
+
+- emmc: rksdmmc@ff520000 {
++ emmc: mmc@ff520000 {
+ compatible = "rockchip,rk3328-dw-mshc",
"rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff520000 0x0 0x4000>;
+- max-frequency = <150000000>;
+- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
+- clock-names = "biu", "ciu";
+- fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
++ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++ fifo-depth = <0x100>;
++ max-frequency = <150000000>;
+ status = "disabled";
+ };
+
+ gmac2io: ethernet@ff540000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff540000 0x0 0x10000>;
+- rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
+@@ -461,21 +903,47 @@
+ "pclk_mac";
+ resets = <&cru SRST_GMAC2IO_A>;
+ reset-names = "stmmaceth";
++ rockchip,grf = <&grf>;
++ snps,txpbl = <0x4>;
+ status = "disabled";
+ };
+
+- usb_host0_ehci: usb@ff5c0000 {
+- compatible = "generic-ehci";
+- reg = <0x0 0xff5c0000 0x0 0x10000>;
+- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++ gmac2phy: ethernet@ff550000 {
++ compatible = "rockchip,rk3328-gmac";
++ reg = <0x0 0xff550000 0x0 0x10000>;
++ rockchip,grf = <&grf>;
++ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++ clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
++ <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
++ <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
++ <&cru SCLK_MAC2PHY_OUT>;
++ clock-names = "stmmaceth", "mac_clk_rx",
++ "mac_clk_tx", "clk_mac_ref",
++ "aclk_mac", "pclk_mac",
++ "clk_macphy";
++ resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
++ reset-names = "stmmaceth", "mac-phy";
++ phy-mode = "rmii";
++ phy-handle = <&phy>;
++ snps,txpbl = <0x4>;
+ status = "disabled";
+- };
+
+- usb_host0_ohci: usb@ff5d0000 {
+- compatible = "generic-ohci";
+- reg = <0x0 0xff5d0000 0x0 0x10000>;
+- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+- status = "disabled";
++ mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy: phy@0 {
++ compatible = "ethernet-phy-id1234.d400",
"ethernet-phy-ieee802.3-c22";
++ reg = <0>;
++ clocks = <&cru SCLK_MAC2PHY_OUT>;
++ resets = <&cru SRST_MACPHY>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
++ phy-is-integrated;
++ };
++ };
+ };
+
+ usb20_otg: usb@ff580000 {
+@@ -483,23 +951,38 @@
+ "snps,dwc2";
+ reg = <0x0 0xff580000 0x0 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+- hnp-srp-disable;
++ clocks = <&cru HCLK_OTG>;
++ clock-names = "otg";
+ dr_mode = "otg";
++ g-np-tx-fifo-size = <16>;
++ g-rx-fifo-size = <280>;
++ g-tx-fifo-size = <256 128 128 64 32 16>;
++ phys = <&u2phy_otg>;
++ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+- sdmmc_ext: rksdmmc@ff5f0000 {
+- compatible = "rockchip,rk3328-dw-mshc",
"rockchip,rk3288-dw-mshc";
+- reg = <0x0 0xff5f0000 0x0 0x4000>;
+- max-frequency = <150000000>;
+- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+- clock-names = "biu", "ciu";
+- fifo-depth = <0x100>;
+- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++ usb_host0_ehci: usb@ff5c0000 {
++ compatible = "generic-ehci";
++ reg = <0x0 0xff5c0000 0x0 0x10000>;
++ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru HCLK_HOST0>, <&u2phy>;
++ phys = <&u2phy_host>;
++ phy-names = "usb";
+ status = "disabled";
+ };
+
+- gic: interrupt-controller@ffb70000 {
++ usb_host0_ohci: usb@ff5d0000 {
++ compatible = "generic-ohci";
++ reg = <0x0 0xff5d0000 0x0 0x10000>;
++ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru HCLK_HOST0>, <&u2phy>;
++ phys = <&u2phy_host>;
++ phy-names = "usb";
++ status = "disabled";
++ };
++
++ gic: interrupt-controller@ff811000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+@@ -647,812 +1130,705 @@
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+- rockchip,pins =
+- <2 24 RK_FUNC_1 &pcfg_pull_none>,
+- <2 25 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
++ <2 RK_PD1 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+- rockchip,pins =
+- <2 4 RK_FUNC_2 &pcfg_pull_none>,
+- <2 5 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
++ <2 RK_PA5 2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+- rockchip,pins =
+- <2 13 RK_FUNC_1 &pcfg_pull_none>,
+- <2 14 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
++ <2 RK_PB6 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+- rockchip,pins =
+- <0 5 RK_FUNC_2 &pcfg_pull_none>,
+- <0 6 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
++ <0 RK_PA6 2 &pcfg_pull_none>;
+ };
+ i2c3_gpio: i2c3-gpio {
+ rockchip,pins =
+- <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
+- <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
++ <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
++ <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hdmi_i2c {
+ hdmii2c_xfer: hdmii2c-xfer {
++ rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
++ <0 RK_PA6 1 &pcfg_pull_none>;
++ };
++ };
++
++ pdm-0 {
++ pdmm0_clk: pdmm0-clk {
++ rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
++ };
++
++ pdmm0_fsync: pdmm0-fsync {
++ rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
++ };
++
++ pdmm0_sdi0: pdmm0-sdi0 {
++ rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
++ };
++
++ pdmm0_sdi1: pdmm0-sdi1 {
++ rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
++ };
++
++ pdmm0_sdi2: pdmm0-sdi2 {
++ rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
++ };
++
++ pdmm0_sdi3: pdmm0-sdi3 {
++ rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
++ };
++
++ pdmm0_clk_sleep: pdmm0-clk-sleep {
+ rockchip,pins =
+- <0 5 RK_FUNC_1 &pcfg_pull_none>,
+- <0 6 RK_FUNC_1 &pcfg_pull_none>;
++ <2 RK_PC2 RK_FUNC_GPIO
&pcfg_input_high>;
+ };
++
++ pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
++ rockchip,pins =
++ <2 RK_PC3 RK_FUNC_GPIO
&pcfg_input_high>;
++ };
++
++ pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
++ rockchip,pins =
++ <2 RK_PC4 RK_FUNC_GPIO
&pcfg_input_high>;
++ };
++
++ pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
++ rockchip,pins =
++ <2 RK_PC5 RK_FUNC_GPIO
&pcfg_input_high>;
++ };
++
++ pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
++ rockchip,pins =
++ <2 RK_PC6 RK_FUNC_GPIO
&pcfg_input_high>;
++ };
++
++ pdmm0_fsync_sleep: pdmm0-fsync-sleep {
++ rockchip,pins =
++ <2 RK_PC7 RK_FUNC_GPIO
&pcfg_input_high>;
++ };
+ };
+
++ tsadc {
++ otp_gpio: otp-gpio {
++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO
&pcfg_pull_none>;
++ };
++
++ otp_out: otp-out {
++ rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
++ };
++ };
++
+ uart0 {
+ uart0_xfer: uart0-xfer {
+- rockchip,pins =
+- <1 9 RK_FUNC_1 &pcfg_pull_up>,
+- <1 8 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
++ <1 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+- rockchip,pins =
+- <1 11 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+- rockchip,pins =
+- <1 10 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ uart0_rts_gpio: uart0-rts-gpio {
+- rockchip,pins =
+- <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+- rockchip,pins =
+- <3 4 RK_FUNC_4 &pcfg_pull_up>,
+- <3 6 RK_FUNC_4 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
++ <3 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+- rockchip,pins =
+- <3 7 RK_FUNC_4 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+- rockchip,pins =
+- <3 5 RK_FUNC_4 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ uart1_rts_gpio: uart1-rts-gpio {
+- rockchip,pins =
+- <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+ };
+
+ uart2-0 {
+ uart2m0_xfer: uart2m0-xfer {
+- rockchip,pins =
+- <1 0 RK_FUNC_2 &pcfg_pull_up>,
+- <1 1 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
++ <1 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2-1 {
+ uart2m1_xfer: uart2m1-xfer {
+- rockchip,pins =
+- <2 0 RK_FUNC_1 &pcfg_pull_up>,
+- <2 1 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
++ <2 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ spi0-0 {
+ spi0m0_clk: spi0m0-clk {
+- rockchip,pins =
+- <2 8 RK_FUNC_1 &pcfg_pull_up>;
++ rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
+ };
+
+ spi0m0_cs0: spi0m0-cs0 {
+- rockchip,pins =
+- <2 11 RK_FUNC_1 &pcfg_pull_up>;
++ rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
+ };
+
+ spi0m0_tx: spi0m0-tx {
+- rockchip,pins =
+- <2 9 RK_FUNC_1 &pcfg_pull_up>;
++ rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
+ };
+
+ spi0m0_rx: spi0m0-rx {
+- rockchip,pins =
+- <2 10 RK_FUNC_1 &pcfg_pull_up>;
++ rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
+ };
+
+ spi0m0_cs1: spi0m0-cs1 {
+- rockchip,pins =
+- <2 12 RK_FUNC_1 &pcfg_pull_up>;
++ rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
+ };
+ };
+
+ spi0-1 {
+ spi0m1_clk: spi0m1-clk {
+- rockchip,pins =
+- <3 23 RK_FUNC_2 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
+ };
+
+ spi0m1_cs0: spi0m1-cs0 {
+- rockchip,pins =
+- <3 26 RK_FUNC_2 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
+ };
+
+ spi0m1_tx: spi0m1-tx {
+- rockchip,pins =
+- <3 25 RK_FUNC_2 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
+ };
+
+ spi0m1_rx: spi0m1-rx {
+- rockchip,pins =
+- <3 24 RK_FUNC_2 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
+ };
+
+ spi0m1_cs1: spi0m1-cs1 {
+- rockchip,pins =
+- <3 27 RK_FUNC_2 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
+ };
+ };
+
+ spi0-2 {
+ spi0m2_clk: spi0m2-clk {
+- rockchip,pins =
+- <3 0 RK_FUNC_4 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
+ };
+
+ spi0m2_cs0: spi0m2-cs0 {
+- rockchip,pins =
+- <3 8 RK_FUNC_3 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
+ };
+
+ spi0m2_tx: spi0m2-tx {
+- rockchip,pins =
+- <3 1 RK_FUNC_4 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
+ };
+
+ spi0m2_rx: spi0m2-rx {
+- rockchip,pins =
+- <3 2 RK_FUNC_4 &pcfg_pull_up>;
++ rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
+ };
+ };
+
+ i2s1 {
+ i2s1_mclk: i2s1-mclk {
+- rockchip,pins =
+- <2 15 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sclk: i2s1-sclk {
+- rockchip,pins =
+- <2 18 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ i2s1_lrckrx: i2s1-lrckrx {
+- rockchip,pins =
+- <2 16 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ i2s1_lrcktx: i2s1-lrcktx {
+- rockchip,pins =
+- <2 17 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdi: i2s1-sdi {
+- rockchip,pins =
+- <2 19 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdo: i2s1-sdo {
+- rockchip,pins =
+- <2 23 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio1: i2s1-sdio1 {
+- rockchip,pins =
+- <2 20 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio2: i2s1-sdio2 {
+- rockchip,pins =
+- <2 21 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio3: i2s1-sdio3 {
+- rockchip,pins =
+- <2 22 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
+ };
+
+ i2s1_sleep: i2s1-sleep {
+ rockchip,pins =
+- <2 15 RK_FUNC_GPIO &pcfg_input_high>,
+- <2 16 RK_FUNC_GPIO &pcfg_input_high>,
+- <2 17 RK_FUNC_GPIO &pcfg_input_high>,
+- <2 18 RK_FUNC_GPIO &pcfg_input_high>,
+- <2 19 RK_FUNC_GPIO &pcfg_input_high>,
+- <2 20 RK_FUNC_GPIO &pcfg_input_high>,
+- <2 21 RK_FUNC_GPIO &pcfg_input_high>,
+- <2 22 RK_FUNC_GPIO &pcfg_input_high>,
+- <2 23 RK_FUNC_GPIO &pcfg_input_high>;
++ <2 RK_PB7 RK_FUNC_GPIO
&pcfg_input_high>,
++ <2 RK_PC0 RK_FUNC_GPIO
&pcfg_input_high>,
++ <2 RK_PC1 RK_FUNC_GPIO
&pcfg_input_high>,
++ <2 RK_PC2 RK_FUNC_GPIO
&pcfg_input_high>,
++ <2 RK_PC3 RK_FUNC_GPIO
&pcfg_input_high>,
++ <2 RK_PC4 RK_FUNC_GPIO
&pcfg_input_high>,
++ <2 RK_PC5 RK_FUNC_GPIO
&pcfg_input_high>,
++ <2 RK_PC6 RK_FUNC_GPIO
&pcfg_input_high>,
++ <2 RK_PC7 RK_FUNC_GPIO
&pcfg_input_high>;
+ };
+ };
+
+ i2s2-0 {
+ i2s2m0_mclk: i2s2m0-mclk {
+- rockchip,pins =
+- <1 21 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sclk: i2s2m0-sclk {
+- rockchip,pins =
+- <1 22 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_lrckrx: i2s2m0-lrckrx {
+- rockchip,pins =
+- <1 26 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_lrcktx: i2s2m0-lrcktx {
+- rockchip,pins =
+- <1 23 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sdi: i2s2m0-sdi {
+- rockchip,pins =
+- <1 24 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sdo: i2s2m0-sdo {
+- rockchip,pins =
+- <1 25 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sleep: i2s2m0-sleep {
+ rockchip,pins =
+- <1 21 RK_FUNC_GPIO &pcfg_input_high>,
+- <1 22 RK_FUNC_GPIO &pcfg_input_high>,
+- <1 26 RK_FUNC_GPIO &pcfg_input_high>,
+- <1 23 RK_FUNC_GPIO &pcfg_input_high>,
+- <1 24 RK_FUNC_GPIO &pcfg_input_high>,
+- <1 25 RK_FUNC_GPIO &pcfg_input_high>;
++ <1 RK_PC5 RK_FUNC_GPIO
&pcfg_input_high>,
++ <1 RK_PC6 RK_FUNC_GPIO
&pcfg_input_high>,
++ <1 RK_PD2 RK_FUNC_GPIO
&pcfg_input_high>,
++ <1 RK_PC7 RK_FUNC_GPIO
&pcfg_input_high>,
++ <1 RK_PD0 RK_FUNC_GPIO
&pcfg_input_high>,
++ <1 RK_PD1 RK_FUNC_GPIO
&pcfg_input_high>;
+ };
+ };
+
+ i2s2-1 {
+ i2s2m1_mclk: i2s2m1-mclk {
+- rockchip,pins =
+- <1 21 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sclk: i2s2m1-sclk {
+- rockchip,pins =
+- <3 0 RK_FUNC_6 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_lrckrx: i2sm1-lrckrx {
+- rockchip,pins =
+- <3 8 RK_FUNC_6 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_lrcktx: i2s2m1-lrcktx {
+- rockchip,pins =
+- <3 8 RK_FUNC_4 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sdi: i2s2m1-sdi {
+- rockchip,pins =
+- <3 2 RK_FUNC_6 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sdo: i2s2m1-sdo {
+- rockchip,pins =
+- <3 1 RK_FUNC_6 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sleep: i2s2m1-sleep {
+ rockchip,pins =
+- <1 21 RK_FUNC_GPIO &pcfg_input_high>,
+- <3 0 RK_FUNC_GPIO &pcfg_input_high>,
+- <3 8 RK_FUNC_GPIO &pcfg_input_high>,
+- <3 2 RK_FUNC_GPIO &pcfg_input_high>,
+- <3 1 RK_FUNC_GPIO &pcfg_input_high>;
++ <1 RK_PC5 RK_FUNC_GPIO
&pcfg_input_high>,
++ <3 RK_PA0 RK_FUNC_GPIO
&pcfg_input_high>,
++ <3 RK_PB0 RK_FUNC_GPIO
&pcfg_input_high>,
++ <3 RK_PA2 RK_FUNC_GPIO
&pcfg_input_high>,
++ <3 RK_PA1 RK_FUNC_GPIO
&pcfg_input_high>;
+ };
+ };
+
+ spdif-0 {
+ spdifm0_tx: spdifm0-tx {
+- rockchip,pins =
+- <0 27 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
+ };
+ };
+
+ spdif-1 {
+ spdifm1_tx: spdifm1-tx {
+- rockchip,pins =
+- <2 17 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ spdif-2 {
+ spdifm2_tx: spdifm2-tx {
+- rockchip,pins =
+- <0 2 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0-0 {
+ sdmmc0m0_pwren: sdmmc0m0-pwren {
+- rockchip,pins =
+- <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
++ rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0m0_gpio: sdmmc0m0-gpio {
+- rockchip,pins =
+- <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
++ rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO
&pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0-1 {
+ sdmmc0m1_pwren: sdmmc0m1-pwren {
+- rockchip,pins =
+- <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
++ rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0m1_gpio: sdmmc0m1-gpio {
+- rockchip,pins =
+- <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
++ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO
&pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+- rockchip,pins =
+- <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
++ rockchip,pins = <1 RK_PA6 1
&pcfg_pull_none_8ma>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+- rockchip,pins =
+- <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
++ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+- rockchip,pins =
+- <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
++ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_wrprt: sdmmc0-wrprt {
+- rockchip,pins =
+- <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
++ rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus1: sdmmc0-bus1 {
+- rockchip,pins =
+- <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
++ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+- rockchip,pins =
+- <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
+- <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
+- <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
+- <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
++ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
++ <1 RK_PA1 1 &pcfg_pull_up_8ma>,
++ <1 RK_PA2 1 &pcfg_pull_up_8ma>,
++ <1 RK_PA3 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc0_gpio: sdmmc0-gpio {
+ rockchip,pins =
+- <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
++ <1 RK_PA6 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PA4 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PA5 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PA7 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PA3 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PA2 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PA1 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PA0 RK_FUNC_GPIO
&pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+- rockchip,pins =
+- <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
++ rockchip,pins = <3 RK_PA2 3
&pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+- rockchip,pins =
+- <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
++ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_wrprt: sdmmc0ext-wrprt {
+- rockchip,pins =
+- <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
++ rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_dectn: sdmmc0ext-dectn {
+- rockchip,pins =
+- <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
++ rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_bus1: sdmmc0ext-bus1 {
+- rockchip,pins =
+- <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
++ rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+- <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
+- <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
+- <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
+- <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
++ <3 RK_PA4 3 &pcfg_pull_up_4ma>,
++ <3 RK_PA5 3 &pcfg_pull_up_4ma>,
++ <3 RK_PA6 3 &pcfg_pull_up_4ma>,
++ <3 RK_PA7 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_gpio: sdmmc0ext-gpio {
+ rockchip,pins =
+- <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
++ <3 RK_PA0 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <3 RK_PA1 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <3 RK_PA2 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <3 RK_PA3 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <3 RK_PA4 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <3 RK_PA5 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <3 RK_PA6 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <3 RK_PA7 RK_FUNC_GPIO
&pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc1 {
+ sdmmc1_clk: sdmmc1-clk {
+- rockchip,pins =
+- <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
++ rockchip,pins = <1 RK_PB4 1
&pcfg_pull_none_8ma>;
+ };
+
+ sdmmc1_cmd: sdmmc1-cmd {
+- rockchip,pins =
+- <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
++ rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_pwren: sdmmc1-pwren {
+- rockchip,pins =
+- <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
++ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_wrprt: sdmmc1-wrprt {
+- rockchip,pins =
+- <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
++ rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_dectn: sdmmc1-dectn {
+- rockchip,pins =
+- <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
++ rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_bus1: sdmmc1-bus1 {
+- rockchip,pins =
+- <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
++ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_bus4: sdmmc1-bus4 {
+- rockchip,pins =
+- <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
+- <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
+- <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
+- <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
++ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
++ <1 RK_PB7 1 &pcfg_pull_up_8ma>,
++ <1 RK_PC0 1 &pcfg_pull_up_8ma>,
++ <1 RK_PC1 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_gpio: sdmmc1-gpio {
+ rockchip,pins =
+- <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+- <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
++ <1 RK_PB4 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PB5 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PB6 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PB7 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PC0 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PC1 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PC2 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PC3 RK_FUNC_GPIO
&pcfg_pull_up_4ma>,
++ <1 RK_PC4 RK_FUNC_GPIO
&pcfg_pull_up_4ma>;
+ };
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+- rockchip,pins =
+- <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
++ rockchip,pins = <3 RK_PC5 2
&pcfg_pull_none_12ma>;
+ };
+
+ emmc_cmd: emmc-cmd {
+- rockchip,pins =
+- <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
++ rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_pwren: emmc-pwren {
+- rockchip,pins =
+- <3 22 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
+ };
+
+ emmc_rstnout: emmc-rstnout {
+- rockchip,pins =
+- <3 20 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ emmc_bus1: emmc-bus1 {
+- rockchip,pins =
+- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
++ rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_bus4: emmc-bus4 {
+ rockchip,pins =
+- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
++ <0 RK_PA7 2 &pcfg_pull_up_12ma>,
++ <2 RK_PD4 2 &pcfg_pull_up_12ma>,
++ <2 RK_PD5 2 &pcfg_pull_up_12ma>,
++ <2 RK_PD6 2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
+- <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
++ <0 RK_PA7 2 &pcfg_pull_up_12ma>,
++ <2 RK_PD4 2 &pcfg_pull_up_12ma>,
++ <2 RK_PD5 2 &pcfg_pull_up_12ma>,
++ <2 RK_PD6 2 &pcfg_pull_up_12ma>,
++ <2 RK_PD7 2 &pcfg_pull_up_12ma>,
++ <3 RK_PC0 2 &pcfg_pull_up_12ma>,
++ <3 RK_PC1 2 &pcfg_pull_up_12ma>,
++ <3 RK_PC2 2 &pcfg_pull_up_12ma>;
+ };
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+- rockchip,pins =
+- <2 4 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+- rockchip,pins =
+- <2 5 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+- rockchip,pins =
+- <2 6 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwmir {
+ pwmir_pin: pwmir-pin {
+- rockchip,pins =
+- <2 2 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+
+- gmac-0 {
+- rgmiim0_pins: rgmiim0-pins {
+- rockchip,pins =
+- /* mac_txclk */
+- <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
+- /* mac_rxclk */
+- <0 10 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_mdio */
+- <0 11 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_txen */
+- <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
+- /* mac_clk */
+- <0 24 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_rxdv */
+- <0 25 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_mdc */
+- <0 19 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_rxd1 */
+- <0 14 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_rxd0 */
+- <0 15 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_txd1 */
+- <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
+- /* mac_txd0 */
+- <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
+- /* mac_rxd3 */
+- <0 20 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_rxd2 */
+- <0 21 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_txd3 */
+- <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
+- /* mac_txd2 */
+- <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
+- };
+-
+- rmiim0_pins: rmiim0-pins {
+- rockchip,pins =
+- /* mac_mdio */
+- <0 11 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_txen */
+- <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
+- /* mac_clk */
+- <0 24 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_rxer */
+- <0 13 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_rxdv */
+- <0 25 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_mdc */
+- <0 19 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_rxd1 */
+- <0 14 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_rxd0 */
+- <0 15 RK_FUNC_1 &pcfg_pull_none>,
+- /* mac_txd1 */
+- <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
+- /* mac_txd0 */
+- <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
+- };
+- };
+-
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+ /* mac_txclk */
+- <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PB4 2 &pcfg_pull_none_8ma>,
+ /* mac_rxclk */
+- <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PB5 2 &pcfg_pull_none_4ma>,
+ /* mac_mdio */
+- <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PC3 2 &pcfg_pull_none_4ma>,
+ /* mac_txen */
+- <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PD1 2 &pcfg_pull_none_8ma>,
+ /* mac_clk */
+- <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PC5 2 &pcfg_pull_none_4ma>,
+ /* mac_rxdv */
+- <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PC6 2 &pcfg_pull_none_4ma>,
+ /* mac_mdc */
+- <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PC7 2 &pcfg_pull_none_4ma>,
+ /* mac_rxd1 */
+- <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PB2 2 &pcfg_pull_none_4ma>,
+ /* mac_rxd0 */
+- <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PB3 2 &pcfg_pull_none_4ma>,
+ /* mac_txd1 */
+- <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PB0 2 &pcfg_pull_none_8ma>,
+ /* mac_txd0 */
+- <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PB1 2 &pcfg_pull_none_8ma>,
+ /* mac_rxd3 */
+- <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PB6 2 &pcfg_pull_none_4ma>,
+ /* mac_rxd2 */
+- <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PB7 2 &pcfg_pull_none_4ma>,
+ /* mac_txd3 */
+- <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PC0 2 &pcfg_pull_none_8ma>,
+ /* mac_txd2 */
+- <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PC1 2 &pcfg_pull_none_8ma>,
+
+ /* mac_txclk */
+- <0 8 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PB0 1 &pcfg_pull_none_8ma>,
+ /* mac_txen */
+- <0 12 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PB4 1 &pcfg_pull_none_8ma>,
+ /* mac_clk */
+- <0 24 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PD0 1 &pcfg_pull_none_4ma>,
+ /* mac_txd1 */
+- <0 16 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PC0 1 &pcfg_pull_none_8ma>,
+ /* mac_txd0 */
+- <0 17 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PC1 1 &pcfg_pull_none_8ma>,
+ /* mac_txd3 */
+- <0 23 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PC7 1 &pcfg_pull_none_8ma>,
+ /* mac_txd2 */
+- <0 22 RK_FUNC_1 &pcfg_pull_none>;
++ <0 RK_PC6 1 &pcfg_pull_none_8ma>;
+ };
+
+ rmiim1_pins: rmiim1-pins {
+ rockchip,pins =
+ /* mac_mdio */
+- <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+- <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PD1 2 &pcfg_pull_none_12ma>,
+ /* mac_clk */
+- <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
+ /* mac_rxer */
+- <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PD0 2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+- <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PC6 2 &pcfg_pull_none_2ma>,
+ /* mac_mdc */
+- <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+- <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PB2 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd0 */
+- <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
++ <1 RK_PB3 2 &pcfg_pull_none_2ma>,
+ /* mac_txd1 */
+- <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PB0 2 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+- <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
++ <1 RK_PB1 2 &pcfg_pull_none_12ma>,
+
+ /* mac_mdio */
+- <0 11 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PB3 1 &pcfg_pull_none>,
+ /* mac_txen */
+- <0 12 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PB4 1 &pcfg_pull_none>,
+ /* mac_clk */
+- <0 24 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PD0 1 &pcfg_pull_none>,
+ /* mac_mdc */
+- <0 19 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PC3 1 &pcfg_pull_none>,
+ /* mac_txd1 */
+- <0 16 RK_FUNC_1 &pcfg_pull_none>,
++ <0 RK_PC0 1 &pcfg_pull_none>,
+ /* mac_txd0 */
+- <0 17 RK_FUNC_1 &pcfg_pull_none>;
++ <0 RK_PC1 1 &pcfg_pull_none>;
+ };
+ };
+
+ gmac2phy {
+- fephyled_speed100: fephyled-speed100 {
+- rockchip,pins =
+- <0 31 RK_FUNC_1 &pcfg_pull_none>;
+- };
+-
+ fephyled_speed10: fephyled-speed10 {
+- rockchip,pins =
+- <0 30 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ fephyled_duplex: fephyled-duplex {
+- rockchip,pins =
+- <0 30 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+- fephyled_rxm0: fephyled-rxm0 {
+- rockchip,pins =
+- <0 29 RK_FUNC_1 &pcfg_pull_none>;
+- };
+-
+- fephyled_txm0: fephyled-txm0 {
+- rockchip,pins =
+- <0 29 RK_FUNC_2 &pcfg_pull_none>;
+- };
+-
+- fephyled_linkm0: fephyled-linkm0 {
+- rockchip,pins =
+- <0 28 RK_FUNC_1 &pcfg_pull_none>;
+- };
+-
+ fephyled_rxm1: fephyled-rxm1 {
+- rockchip,pins =
+- <2 25 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ fephyled_txm1: fephyled-txm1 {
+- rockchip,pins =
+- <2 25 RK_FUNC_3 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ fephyled_linkm1: fephyled-linkm1 {
+- rockchip,pins =
+- <2 24 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc_pin {
+ tsadc_int: tsadc-int {
+- rockchip,pins =
+- <2 13 RK_FUNC_2 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
+ };
+ tsadc_gpio: tsadc-gpio {
+- rockchip,pins =
+- <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+ };
+
+ hdmi_pin {
+ hdmi_cec: hdmi-cec {
+- rockchip,pins =
+- <0 3 RK_FUNC_1 &pcfg_pull_none>;
++ rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ hdmi_hpd: hdmi-hpd {
+- rockchip,pins =
+- <0 4 RK_FUNC_1 &pcfg_pull_down>;
++ rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
+ };
+ };
+
+@@ -1460,29 +1836,29 @@
+ dvp_d2d9_m0:dvp-d2d9-m0 {
+ rockchip,pins =
+ /* cif_d0 */
+- <3 4 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA4 2 &pcfg_pull_none>,
+ /* cif_d1 */
+- <3 5 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* cif_d2 */
+- <3 6 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA6 2 &pcfg_pull_none>,
+ /* cif_d3 */
+- <3 7 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA7 2 &pcfg_pull_none>,
+ /* cif_d4 */
+- <3 8 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PB0 2 &pcfg_pull_none>,
+ /* cif_d5m0 */
+- <3 9 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PB1 2 &pcfg_pull_none>,
+ /* cif_d6m0 */
+- <3 10 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PB2 2 &pcfg_pull_none>,
+ /* cif_d7m0 */
+- <3 11 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PB3 2 &pcfg_pull_none>,
+ /* cif_href */
+- <3 1 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA1 2 &pcfg_pull_none>,
+ /* cif_vsync */
+- <3 0 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA0 2 &pcfg_pull_none>,
+ /* cif_clkoutm0 */
+- <3 3 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA3 2 &pcfg_pull_none>,
+ /* cif_clkin */
+- <3 2 RK_FUNC_2 &pcfg_pull_none>;
++ <3 RK_PA2 2 &pcfg_pull_none>;
+ };
+ };
+
+@@ -1490,29 +1866,29 @@
+ dvp_d2d9_m1:dvp-d2d9-m1 {
+ rockchip,pins =
+ /* cif_d0 */
+- <3 4 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA4 2 &pcfg_pull_none>,
+ /* cif_d1 */
+- <3 5 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* cif_d2 */
+- <3 6 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA6 2 &pcfg_pull_none>,
+ /* cif_d3 */
+- <3 7 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA7 2 &pcfg_pull_none>,
+ /* cif_d4 */
+- <3 8 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PB0 2 &pcfg_pull_none>,
+ /* cif_d5m1 */
+- <2 16 RK_FUNC_4 &pcfg_pull_none>,
++ <2 RK_PC0 4 &pcfg_pull_none>,
+ /* cif_d6m1 */
+- <2 17 RK_FUNC_4 &pcfg_pull_none>,
++ <2 RK_PC1 4 &pcfg_pull_none>,
+ /* cif_d7m1 */
+- <2 18 RK_FUNC_4 &pcfg_pull_none>,
++ <2 RK_PC2 4 &pcfg_pull_none>,
+ /* cif_href */
+- <3 1 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA1 2 &pcfg_pull_none>,
+ /* cif_vsync */
+- <3 0 RK_FUNC_2 &pcfg_pull_none>,
++ <3 RK_PA0 2 &pcfg_pull_none>,
+ /* cif_clkoutm1 */
+- <2 15 RK_FUNC_4 &pcfg_pull_none>,
++ <2 RK_PB7 4 &pcfg_pull_none>,
+ /* cif_clkin */
+- <3 2 RK_FUNC_2 &pcfg_pull_none>;
++ <3 RK_PA2 2 &pcfg_pull_none>;
+ };
+ };
+ };
diff --git a/sysutils/u-boot/patches/patch-configs_nanopi_r2s-rk3328_defconfig
b/sysutils/u-boot/patches/patch-configs_nanopi_r2s-rk3328_defconfig
new file mode 100644
index 00000000000..951f729d232
--- /dev/null
+++ b/sysutils/u-boot/patches/patch-configs_nanopi_r2s-rk3328_defconfig
@@ -0,0 +1,106 @@
+$OpenBSD$
+
+Index: configs/nanopi_r2s-rk3328_defconfig
+--- configs/nanopi_r2s-rk3328_defconfig.orig
++++ configs/nanopi_r2s-rk3328_defconfig
+@@ -0,0 +1,100 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x00200000
++CONFIG_SPL_GPIO_SUPPORT=y
++CONFIG_ROCKCHIP_RK3328=y
++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
++CONFIG_TPL_LIBCOMMON_SUPPORT=y
++CONFIG_TPL_LIBGENERIC_SUPPORT=y
++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
++CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_SPL_STACK_R_ADDR=0x600000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_DEBUG_UART_BASE=0xFF130000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_SMBIOS_PRODUCT_NAME="nanopi_r2s_rk3328"
++CONFIG_DEBUG_UART=y
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
++CONFIG_MISC_INIT_R=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_I2C_SUPPORT=y
++CONFIG_SPL_POWER_SUPPORT=y
++CONFIG_SPL_ATF=y
++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
++CONFIG_TPL_OF_PLATDATA=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_TPL_DM=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_FASTBOOT_BUF_ADDR=0x800800
++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_SF_DEFAULT_SPEED=20000000
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PHY=y
++CONFIG_PINCTRL=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_SPL_DM_REGULATOR=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_SPL_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_BAUDRATE=115200
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYSRESET=y
++# CONFIG_TPL_SYSRESET is not set
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_GENERIC=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_GADGET is not set
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_SPL_TINY_MEMSET=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y
++CONFIG_SMBIOS_MANUFACTURER="friendlyelec"
diff --git
a/sysutils/u-boot/patches/patch-include_dt-bindings_power_rk3328-power_h
b/sysutils/u-boot/patches/patch-include_dt-bindings_power_rk3328-power_h
new file mode 100644
index 00000000000..c7834356eaf
--- /dev/null
+++ b/sysutils/u-boot/patches/patch-include_dt-bindings_power_rk3328-power_h
@@ -0,0 +1,25 @@
+$OpenBSD$
+
+Index: include/dt-bindings/power/rk3328-power.h
+--- include/dt-bindings/power/rk3328-power.h.orig
++++ include/dt-bindings/power/rk3328-power.h
+@@ -0,0 +1,19 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__
++#define __DT_BINDINGS_POWER_RK3328_POWER_H__
++
++/**
++ * RK3328 idle id Summary.
++ */
++#define RK3328_PD_CORE 0
++#define RK3328_PD_GPU 1
++#define RK3328_PD_BUS 2
++#define RK3328_PD_MSCH 3
++#define RK3328_PD_PERI 4
++#define RK3328_PD_VIDEO 5
++#define RK3328_PD_HEVC 6
++#define RK3328_PD_SYS 7
++#define RK3328_PD_VPU 8
++#define RK3328_PD_VIO 9
++
++#endif
