On 08/12/2014 05:32 PM, Robert Jordens wrote:
> n = core.coerce(1.2345*ns) # [n] = core.cycle
> for i in range(1000):
> core.delay(n)
> f = dds.coerce(345*MHz)
> t = dds.coerce(core.coerce(1000*n, to=ns))
> phi = dds.coerce(f*t, to=rad) # [f*t] = dds.ftw*dds.cycle
It's implementable right now as:
# n is RTIO cycle count (dimensionless int64)
n = time_to_cycles(1.2345*ns)
for i in range(1000):
# cycles_to_time is exact (uses rational arithmetic)
# compiler optimizes to "now += n" (int64 operation)
delay(cycles_to_time(n))
# ftw is raw int32 frequency tuning word
ftw = self.dds.frequency_to_ftw(345*MHz)
# f is exact (rational) frequency in Hz
f = self.dds.ftw_to_frequency(ftw)
# phi is in turns, rational number
phi = 1000*cycles_to_time(n)*f
When running on the device (running on the host in the interpreter is
also possible), the transforms turn that into the following code before
passing it to py2llvm (with 1GHz RTIO and DDS clocks):
now = int64(0)
n = int64(1)
for i in range(1000):
now += n
frequency_to_ftw_return = 1481763717
ftw = frequency_to_ftw_return
ftw_to_frequency_return = ((ftw * Fraction(1000000000, 1)) / 4294967296)
f = ftw_to_frequency_return
phi = ((1000 * (n * Fraction(1, 1000000000))) * f)
The obvious performance optimization here is to have the constant
folding transform work across statements.
Since there is only one FUD sampling by the DDS chip every 8 RTIO/DDS
cycles, this phase difference computation is correct only if "now" is
increased by a multiple of 8 in the block of code.
Sébastien
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