Hi, I've been doing some hardware tests on the QC2 AD9914 DDS system. Many things are working (tested using the runtime test mode): * basic read/write of the registers, reset values match the datasheet * 100000 cycles of ddstest * selection of different slots on the backplane * reset - a modified register returns to its default value * FUD (aka IO_UPDATE) - the SYNC_CLK output is correctly toggling at 125MHz (3GHz/24), and I can turn it on and off using the "SYNC_CLK enable" bit of CFR2 followed by FUD.
I'm clocking the DDS at 3GHz, using a SynthNV locked to the 10MHz output generated by the ARTIQ SoC on USER_GPIO_P, itself locked to the 125MHz internal RTIO clock. There are some problems though, which may be due to a hardware issue: The DDS output is stuck at zero (including at the input of the ERA-4 amplifier), and SYNC_OUT is not toggling. The current drawn on 1.8V (analog + digital) is abnormal: 138mA immediately upon power up (before interaction with the FPGA) which goes to 170mA after ddsinit. The current draw is not affected by FTW programming, but setting all power-down bits in CFR1 diminishes it significantly. According to the datasheet, the 1.8V current should be >400mA. What is the current drawn by other boards, immediately upon power up and while the DDS is properly generating a signal? Both 1.8V points on JP2 are powered. Current on 3.3V is ~500mA which is consistent with the datasheet. Could you: * let me know what the normal 1.8V current values are. * confirm that register read/writes work on your hardware (ddstest). * test the rest of AD9914 support in ARTIQ as the problems I'm experiencing might be due to a faulty DDS board. Do you have ideas about what the problem could be? ddsinit does this: https://github.com/m-labs/artiq/blob/fba05531f456ba4d0f2b47d241bb039ab66ba930/soc/runtime/test_mode.c#L240 Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
