>The DDS output is stuck at zero (including at the input of the ERA-4
>amplifier), and SYNC_OUT is not toggling.
Have the amplitude registers been programmed? I've noticed on our AD9914 eval
board that profile 0 defaults to 0 before they're programmed. Profiles 1 to 7
amplitudes have a somewhat random default starting amplitude value. So profile
0 will not output anything with only a FTW but profiles 1-7 will.
On the eval board that we're currently using, I'm using a 2.4 GHz clock with
about 4 dBm in . Starting the DDS, currents are 3.3V/0.57A and 1.8V/0.11A. The
3.3V current is more or less constant at 0.57 A. I first put in the following
values to the registers,
np.array([0x03, 0x01, 0x05, 0x21, 0x20,
0x01, 0x00, 0x80, 0x09, 0x00,
0x00, 0x01, 0x01, 0x01, 0x02,
0x1B, 0x00, 0x00, 0x08, 0x00])
And clear the DAC cal bit,
np.array([0x03, 0x00, 0x05, 0x21, 0x20])
At this point the current on the 1.8 V is 0.12 A but if I turn on any of the
profile pins it jumps to 0.25 A.
I then programme the FTW for profile 0 to output 1.3 GHz and do an ioupdate.
Current is at 1.8V/0.12A.
Now if I set the profile 0 amplitude to 0.9999 and phase to 0 and do an
ioupdate, the current goes to 0.15 A and I can see the 1.3 GHz output from
profile 0 on the spectrum analyser. Code to set profile frequency, amplitude
and phase is below.
Sincerely,
Raghu
def set_profile_frequency(self, slave_select, profile, input_frequency):
# input_frequency in MHz
quotient = int(2**32*input_frequency/self.clockfrequency)
output_quotient = ('{:0>2x}'.format(11+2*profile) +
'{:0>8x}'.format(quotient))
if len(output_quotient) != 10:
raise AD9914_Exception('frequency')
self.cheetah.start_queue(self.handle, slave_select)
self.cheetah.ch_spi_queue_array(self.handle,
byte_array(output_quotient))
self.cheetah.end_queue(self.handle)
def set_profile_amplitude_phase(self, slave_select, profile,
amplitude, phase):
output_amp = '{:0>4x}'.format(int(amplitude*2**12))
output_phase = '{:0>4x}'.format(int((float(phase)/360)*2**16))
output = '{:0>2x}'.format(12+2*profile) + output_amp + output_phase
self.cheetah.send_array(self.handle, slave_select, byte_array(output))
-----Original Message-----
From: ARTIQ [mailto:[email protected]] On Behalf Of Sébastien
Bourdeauducq
Sent: Saturday, August 22, 2015 3:16 AM
To: [email protected]
Subject: [ARTIQ] AD9914 support status and questions
Hi,
I've been doing some hardware tests on the QC2 AD9914 DDS system. Many things
are working (tested using the runtime test mode):
* basic read/write of the registers, reset values match the datasheet
* 100000 cycles of ddstest
* selection of different slots on the backplane
* reset - a modified register returns to its default value
* FUD (aka IO_UPDATE) - the SYNC_CLK output is correctly toggling at 125MHz
(3GHz/24), and I can turn it on and off using the "SYNC_CLK enable" bit of CFR2
followed by FUD.
I'm clocking the DDS at 3GHz, using a SynthNV locked to the 10MHz output
generated by the ARTIQ SoC on USER_GPIO_P, itself locked to the 125MHz internal
RTIO clock.
There are some problems though, which may be due to a hardware issue:
The DDS output is stuck at zero (including at the input of the ERA-4
amplifier), and SYNC_OUT is not toggling.
The current drawn on 1.8V (analog + digital) is abnormal: 138mA immediately
upon power up (before interaction with the FPGA) which goes to 170mA after
ddsinit. The current draw is not affected by FTW programming, but setting all
power-down bits in CFR1 diminishes it significantly.
According to the datasheet, the 1.8V current should be >400mA. What is the
current drawn by other boards, immediately upon power up and while the DDS is
properly generating a signal?
Both 1.8V points on JP2 are powered. Current on 3.3V is ~500mA which is
consistent with the datasheet.
Could you:
* let me know what the normal 1.8V current values are.
* confirm that register read/writes work on your hardware (ddstest).
* test the rest of AD9914 support in ARTIQ as the problems I'm experiencing
might be due to a faulty DDS board.
Do you have ideas about what the problem could be?
ddsinit does this:
https://github.com/m-labs/artiq/blob/fba05531f456ba4d0f2b47d241bb039ab66ba930/soc/runtime/test_mode.c#L240
Sébastien
_______________________________________________
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
_______________________________________________
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq
