> Note that parallel LVDS can be done with a Artix FPGA, which could be the
> lowest-cost-per-channel option. The largest device is relatively small > compared to Kintex though, so one would have to research whether fabric or > IO is the limiting factor for the number of channels, or if it is roughly > balanced. Artix FPGA also has gigabit transceiver lines and so could be used for JESD204B as well. The difference is that even the highest speed grade in the Artix is limited to 6.6 Gbps transmission. It would still be possible to run 8 channels of output with 312 MHz instantaneous bandwidth using two DAC38J84 chips using 12 lanes (you send 8 lanes to one DAC and 4 lanes to the other, use 2 lanes for synchronization ). There are 16 available GTX (giving you 4 spares) on the largest Artix-7, an XC7A200T-2FFG1156C, which costs $280 apiece (as opposed to $1000 for the XC7K325T Kintex in the -1 speed grade, or $1700 for the -3 speed grade needed for the full 12.5 Gbps data rate). . The hardware could be reprogrammed to run with 6 channels of 660 MHz instantaneous bandwidth or 4 channels of 1.23 GHz instantaneous bandwidth, depending on the desires of the user. This would enable us to satisfy both the desires for ~ 1 GHz instantaneous bandwidth for SC qubit or other fast applications on the same card, and using a much less expensive FPGA. Now your card has a $500 hardware cost for FPGA and DACs instead of $2000. Sebastien, are there other issues with the Artix-7 series that would be problematic for what we want to do? The cost savings are definitely substantial. FPGA size is listed below, we would use the largest one, which is about 2/3 the size of the Kintex 7 on the KC705 board. Best, Daniel [cid:image001.png@01D12E93.2683B110]
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