> There is no particular issue with Artix besides the already mentioned fabric > size and transceiver limitations. Note that JESD204B synchronization does not > require additional transceiver resources, so we have 4 spare ones, not 2. SFP > (for crate-to-crate fiber) and/or the backplane will typically need some -
If we decide to dedicate two transceivers to SFP and backplane, that leaves two potentially open. One nice way to use these would be to add a JESD204B ADC to the same card, as proposed by Dave Leibrandt and others. This would enable the tightest loops for feedback to the DAC outputs. Candidate chips (in my rough order of preference): http://www.ti.com/product/adc16dx370 - use 2 JESD204B lanes @ 6.6 Gbps - get 2 channels of 16-bit DAC at up to 330 MSPS (using Artix-7) - latency 18.5 ADC clock cycles (56 ns at max speed) http://www.ti.com/product/ads42jb69 - use 2 JESD204B lanes @ 3.125 Gbps (limited by chip) - get 2 channels of 16-bit DAC at up to 156 MSPS - this chip has slightly better distortion/spur properties than the previous one - latency 23 ADC clock cycles (147 ns at max speed) http://www.analog.com/en/products/analog-to-digital-converters/ad-converters/ad9683.html - use 2 chips, each with one JESD204B lane @ 5 Gbps (limited by chip) - each chip: one channel of 14-bit DAC at up to 250 MSPS - chip distortion properties are almost the same as the previous 2 ADCs - would need to synchronize the two chips with SYSREF system, feed matched data clocks - latency 36 ADC clock cycles (144 ns at max speed) - this chip features a CMOS output that determines whether the signal magnitude is above or below a programmable threshold value (with a hysteretic threshold to give some noise immunity). Latency for this output is only 7 ADC clock cycles, or 28 ns at max clock speed. This would be a nice feature for people trying to perform ultra-fast feedback on a qubit measurement (e.g. sc qubit folks?). Another option would of course be to use a parallel LVDS ADC instead of a JESD204B model, and there appear to be quite a number of high performance candidates suitable for the task. Best, Daniel _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
