Hello, to allow for FPGA selection and to rush the funding I have done a design study and implemented a basic DSP output channel for the ARTIQ DSP hardware. A 1.25 GS/s, 16 bit, "smart" channel pair would do
o0 = u0 + i0 * a0 * cos(f0 * t + p0) + q1 * a1 * sin(f1 * t + p1) o1 = u1 + q0 * a0 * sin(f0 * t + p0) + i1 * a1 * cos(f1 * t + p1) * u and a are 16 bit cubic spline inteprolators * p are 16 bit constant (non-) interpolators * f are 48 bit linear interpolators * i and q are switches (0 or 1) that allow many different configurations, among them single tone independent, two-tone, single tone iq, and two-tone iq all with independent dc offsets * the inteprolators interpolate at 1/8 output rate, the DUCs output at full rate (effectively). * all designed for 16 bit spline knot duration resolution and scalable spline interpolation clock This uses about 28 kLUT, 14% of a xc7k325t. The timing, parsing, serial link, rtlink, drtio, jdes phy, gearbox, monitoring, digital servo, adc logic will probably add another 10-20 kLUT per channel pair but this is the dominant chunk. This looks good for the xc7a200t or a xc7k325t as the building block and 4 channels (two smart channel pairs). I haven't implemented, benchmarked, or tested the latest X suggestions and design tweaks from article Y in journal Z. Robert. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
