Re DAC clock: presumably, the plan is to distribute a 10MHz (or 100MHz, or whatever) clock with really low close-in phase noise to each MCH, and then from each MCH to the AMCs via the backplane. Why not send this from the AMC to the FMC boards via the FMC connectors? Then, have the FMC board generate the DAC clock using an integer-N PLL. If done properly, an int-N PLL at a couple of GHz is cheap, has a small footprint and will give as good phase noise/phase stability as using an external synth plus coax. The loop filter bandwidth can be low enough to take out any cross-talk from the FMC/backplane. Plus, this way the DAC clock has a well-defined phase relationship to the main system clock (the 10MHz or whatever), which may come in handy for keeping everything synchronised...
> No! The clock coming in will be a sine wave from a low phase noise > oscillator somewhere. The DACs and ADCs will threshold this clock to > determine their sample times. Any amount of crosstalk will distort the clock > signal (adding or subtracting to the voltage at a given time), thus skewing > the time at which the threshold is reached and thus inducing jitter into the > sampling times. This would also hold true even if you have an LVPECL clock > signal, because at frequencies like 2.4 GHz the rise and fall times (~100-200 > ps) are similar to that of a sine wave. Unlike for digital data signals, any > amount of crosstalk will degrade the jitter and/or edge time performance for > a clock signal. Tom
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