Hi You can use the SDRAM controller in PS section of the ZYnQ directly from PL part, the only thing you need is to configure the MMU so it gains access to it. Normally, in my designs I connect another bank of DDR memory directly to PL part and such solution will be used in my CBM board. In case of ZU7 you have 24+4 transceivers, but with ZU11 you have 32+4 ones:) All in compatible package. Greg
-----Original Message----- From: Slichter, Daniel H. (Fed) [mailto:daniel.slich...@nist.gov] Sent: Saturday, April 09, 2016 1:42 AM To: Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>; 'Sébastien Bourdeauducq' <s...@m-labs.hk> Cc: 'Grzegorz Kasprowicz' <kaspr...@gmail.com>; artiq@lists.m-labs.hk Subject: RE: [ARTIQ] FW: initial specification of the project I also think that, however "disgusting" the Zynq is, there are a number of people who might want the additional processing power available in a hard processor. Greg also points out a number of advantages in terms of management of bitstreams in a large-scale experimental setting. On our previous phone conversations with Sebastien, Joe, and Dave Leibrandt, it seemed that using the hard processor on the Zynq would be necessary to be able to talk to a connected SDRAM chip, so there is a little more to it than just treating it as a regular Kintex in terms of connections. However, Sebastien seemed to think that it would not be that difficult to implement things on a Zynq. Sebastien, has this opinion changed? Is the "disgusting" part of Zynq a philosophical objection, or an objection based on the amount of additional work required to implement gateware? Many potential users might prefer having a Zynq. We also discussed the advantages of having 24 gigabit transceivers, instead of 16, in that then we are not reduced to hacks to have gigabit connectivity (e.g. GbE, potentially PCIe, etc) while keeping the possibility of using 8 DAC outputs at their full bandwidth. If this is not a priority, the AD9154 can be run at a reduced instantaneous bandwidth (e.g. higher interpolation rate) or reduced channel count, both of which would be satisfactory for some applications, with only 4 lanes connected. Thus one could connect one FMC with 8 lanes and the other with 4 lanes (4 lanes is all that is needed for 4 channels of ADC at max data rates), and have 4 left over. I proposed this idea back some months ago when we were doing initial discussions. Best, Daniel > -----Original Message----- > From: Grzegorz Kasprowicz [mailto:gkasp...@elka.pw.edu.pl] > Sent: Friday, April 08, 2016 6:00 AM > To: 'Sébastien Bourdeauducq' <s...@m-labs.hk> > Cc: 'Grzegorz Kasprowicz' <kaspr...@gmail.com>; Slichter, Daniel H. > (Fed) <daniel.slich...@nist.gov>; artiq@lists.m-labs.hk > Subject: RE: [ARTIQ] FW: initial specification of the project > > Well, I compared highest speed grades (-3) in large packages :) > XC7K325T- 3FFG900E costs more than ZU11 in similar speed grade. > Personally, I like this disgusting ZynQ stuff. I didn't have any > special troubles to make it running. And it gives very handy feature > of FPGA upgrade over Ethernet :) In this way you can keep all FPGA bit > streams on single nfs server and load them at the startup. > THE CPU and FPGA are independent, so you can boot CPU without the > bitstream, connect to nfs, grab the bitteam and load it. So you can > treat it as CPU which simply loads the FPGA and from programmable > logic you treat it as ordinary Kintex device. > And you get bunch of IOs for free which can be controlled over Ethernet. > In case of complex system it is very desirable because you keep all > the settings in single location and to upgrade it don't have to walk > with programmer from board to board. > We have a system which consists of 22 FPGAs in single box and all FPGA > files are kept on single USB drive. The system is installed in UK and > upgraded once a month and it is real pleasure to work in such manner. > Another system is CMS muon trigger which consists of thousands of > FPGAs and they all are loaded at the startup. It's much easier to keep > control on bitstream versions of individual chips. > The only alternative update channel in MTCA is either JTAG or I2C. > With I2C you need about 30hours to programm the config FLASH. In case > of JTAG, not every MTCA crate has JSM. > Greg > > > -----Original Message----- > From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] > Sent: Friday, April 08, 2016 12:13 PM > To: Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl> > Cc: 'Grzegorz Kasprowicz' <kaspr...@gmail.com>; 'Slichter, Daniel H. (Fed)' > <daniel.slich...@nist.gov>; artiq@lists.m-labs.hk > Subject: Re: [ARTIQ] FW: initial specification of the project > > On Friday, 8 April 2016 11:53:25 AM HKT Grzegorz Kasprowicz wrote: > > Btw, > > ZU11 FPGA costs more or less the same as 7K325 and offers almost > > twice more logic resources. The price of ZU11 is $1,376.00 at 100pcs. > > Since we will buy such quantity for our CBM project (Fair facility > > in GSI), we can use that step pricing in this case as well. > > Even on Digikey in single quantities, 7K325T starts at $898.75 (and > the cheapest one in FF which seems to be recommended for the full > transceiver bandwidth is $1122.50) and we don't have to deal with any > of this disgusting Zynq stuff. > > Sébastien > _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
