On Friday, October 28, 2016 08:49 PM, Jonathan Mizrahi wrote:
In the platform extension file, when I specify the SPI buses, there is a clock subsignal "clk." If I want to have multiple SPI buses that share the same clock, I'm going to need to reference the same clock subsignal in each bus, which means that that specific pin will appear multiple times in the file. Will this cause any problems?
Yes. There will be multiple drivers for the same FPGA pin, and the FPGA tools cannot do anything reasonable with that.
Do I need to do something else to have a shared SPI clock?
The code assumes one clock per bus. There would be a bit of work to do. If you are using the SPI devices one by one, I suggest putting them all on a single RTIO channel and mux/demux MISO/MOSI.
Sébastien _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
