On Friday, October 28, 2016 11:55 PM, Jonathan Mizrahi wrote:
How do you recommend I do that?
Something like:
self.comb += [
mosi_dev1.eq(mosi_spi_core),
mosi_dev2.eq(mosi_spi_core),
miso_spi_core.eq(miso_dev_1 | miso_dev_2)
]
The last line assumes that a non-transmitting device (weakly) pulls down
MISO. If this is not the case, you need to mux using CS instead.
There will also be some subtleties with the tristate.
Sébastien
_______________________________________________
ARTIQ mailing list
https://ssl.serverraum.org/lists/listinfo/artiq