On 2018-08-06, at 16:12:37, Dan Greiner wrote: > I was once asked why the execute exception existed. That is, why not just let > the hardware — or, in this odd case, the firmware — cascade down a chain of > multiple EX instructions, ORing the bits of the R1 field with the subsequent > target instruction, whatever instruction that might be. Aside from there > being absolutely no practical reason for wasting circuits on such folly, ... > You've been there; I haven't, so I bow to your expertise. I wouldn't have guessed whether it's less hardware to detect the special case and throw an exception, or just to do it.
> the answer is obvious ... the EX instruction could target itself, and the CPU > would get its knickers tied into a knot without an exception. > Which is no worse than " B *", provided that the chain is interruptible (set OPSW to point to head of chain and redrive when interrupt is dismissed). I don't recall exactly how PDP-10 handled this. I think it allowed chained EX, interruptible until committed at end of chain. PDP-10 also had multi-level indirect addressing, interruptible until the final resolution of the address. I once tried to create an indirect address chain that touched every virtual page just to see what a page fault loop looked like. Somehow I couldn't get a conclusive result. -- gil
