On 6/7/2020 7:11 AM, Peter Relson wrote:
That limitation is not the case for z/Architecture vector operations.
</snip>
I erred in writing that. Shmuel was of course correct. The "vector
register" is 128 bits (one quadword).
The extent of the "vectorization" depends on the size of the operands.
We use SIMD *heavily* for character-based operations and the speed is
incredible!
Doing 16 operations at once sure is preferable to doing just one! ijs... ;-)
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