> Only if you write into the data areas; > the OP wrote of constants in macros, so the areas should be read-only.
Can someone who knows the hardware architecture definitively confirm or deny that assertion? I always thought there were separate D- and I-cache lines, and so the branch-around technique will cause some D-cache to be flushed and re-loaded, and ultimately flushed and re-loaded again, just to accommodate your one constant. Also, of course, branches are not performance-enhancing. Charles -----Original Message----- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Bernd Oppolzer Sent: Monday, November 8, 2021 1:01 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Base-less macros Am 08.11.2021 um 05:40 schrieb Charles Mills: > +1 > > I have my LOCTR's named CODE and DATA but I agree with the concept: base > register points to the CSECT; CSECT has data and LTORG's first. Hard to get > totally away from base registers, especially if your ARCH does not support > EXR. > > You don't want inline data values that you branch around. They are > cache-killers. Only if you write into the data areas; the OP wrote of constants in macros, so the areas should be read-only.
