On 11/21/23 14:32:27, Tom Marchant wrote:
Modern processors use a 256-byte cache line, with separate caches for instructions and data. A cache line maps to 256 bytes of storage on a 256-byte boundary. There are performance penalties when the same line of storage needs to be in both the instruction cache and the data cache. It has nothing to do with the base register used.
Is it recommended, then, to cache-line align LTORG so instructions and data don't share a cache line. Is there an instruction that will continue to do this for future hardware? -- gil
