My understanding was that instructions and other constants can share a cache line with no interference. Data that is changed, whether instructions or "constants", will require the cache line to be present in the data cache. The separation should be between data that can/will be changed and the data that will not change.
Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone:+1.613.523.5500 x216 Email: weinh...@dkl.com Visit us online at www.DKL.com E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system. ________________________________ From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> on behalf of Pieter Wiid <pw...@mweb.co.za> Sent: November 28, 2023 09:59 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU <ASSEMBLER-LIST@LISTSERV.UGA.EDU> Subject: Re: BAKR/PR and Linkage Convenction I have a PAD macro that takes the alignment as a parameter. It generates nC'P', where "n" is calculated to align on your selected boundary -----Original Message----- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Paul Gilmartin Sent: Tuesday, 21 November 2023 23:50 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BAKR/PR and Linkage Convenction On 11/21/23 14:32:27, Tom Marchant wrote: > Modern processors use a 256-byte cache line, with separate caches for > instructions and data. A cache line maps to 256 bytes of storage on a > 256-byte boundary. > There are performance penalties when the same line of storage needs to > be in both the instruction cache and the data cache. > It has nothing to do with the base register used. > > Is it recommended, then, to cache-line align LTORG so instructions and data don't share a cache line. Is there an instruction that will continue to do this for future hardware? -- gil -- This email has been checked for viruses by Avast antivirus software. www.avast.com<http://www.avast.com>
