2009/10/6 Aditya <aybh...@cmu.edu>: > Hi, > > In my project, I need to be able to change the channel width of Atheros > chips to 5/10/40MHz in the 2.4/5GHz bands. I have gone through the > source code of ath5k and there appear to be places where a "TODO > Half/Quarter width" is written. > Can someone please help me on the changes that need to be made in order > to get this to work? If I use SAMs HAL, what is the API/function call > that I need to make in order to change channel width? > > I understand it is to do with setting the PLL clock frequency which can > be done in reset.c under ath5k_hw_nic_wakeup() by setting > > clock |= AR5K_PHY_PLL_20MHZ; instead of clock |= AR5K_PHY_PLL_44MHZ > and > clock |= AR5K_PHY_PLL_20MHZ; instead of clock |= AR5K_PHY_PLL_40MHZ; > > but is this the only change to be done? As of now, I dont really need a > clean API to get this to work, I just need to run some simple > experiments with channel widths for my project. > > Thanks for your help > regards, > Aditya Bhave
You also need to tweak some more clock settings and modify a few more rf bus settings (search for TODOs inside ath5k source that mention 5/10Mhz channel support and cross refference with Sam's HAL and Legacy HAL). We had a report about 5MHz channels working with just the settings you mentioned but haven't tested it much. Until we have a clean way to set this through cfg80211/nl80211 (which is an ongoing discussion) we wont support 5/10Mhz operation but you can try and let us know. -- GPG ID: 0xD21DB2DB As you read this post global entropy rises. Have Fun ;-) Nick _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
