Le 25/06/2010 22:08, Steve Brown a écrit : > I have a couple of Ubiquity XR9's. They use an AR5413 (168c:001b, ss > 3009:0777) and downconvert to the 900MHz ISM band. The default channel > width is 20MHz and confirmed by my spec analyzer. I'd like to use them > at 10MHz and 5MHz. > > My searching turned up very little. Ubiquity released an unsupported > hack to madwifi that compiles against an old kernel, but the channel > width changes take place in their binary HAL. There also appears to be > support in the madwifi driver (proprietary HAL version 3314) by setting > /proc/sys/dev/wifi0/channelbw, but it doesn't seem to work. The call to > the HAL routine to change the width returns an error. Further, that > support// disappeared in the open HAL version. Nowhere was there any > information on what values go in which regs. > > I see that there are some TO DO comments in the ath5k code for > half/quarter channels. Is this being worked on? > > If not and somebody on the list has the needed info and would be willing > to suffer some dumb questions, I'll try to add it. > > Steve
Hi Steve, Reading ath5k, I gathered the following information : /* * PHY timing register 3 [5112+] */ #define AR5K_PHY_TIMING_3 0x9814 #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 #define AR5K_PHY_TIMING_3_DSC_MAN_S 17 #define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 #define AR5K_PHY_TIMING_3_DSC_EXP_S 13 This describe the mantissa (MAN) and exponent (EXP) of the clock used to compute the center frequency. This value is divided by 2 for 10 MHz channels. /* * PHY PLL (Phase Locked Loop) control register */ #define AR5K_PHY_PLL 0x987c #define AR5K_PHY_PLL_HALF_RATE 0x00000100 #define AR5K_PHY_PLL_QUARTER_RATE 0x00000200 For 802.11a (40MHz PLL), bit AR5K_PHY_PLL_HALF is set to get 10 MHz channels. That's probably the most important register. /* * PHY mode register [5111+] */ #define AR5K_PHY_MODE 0x0a200 /* Register Address */ #define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */ #define AR5K_PHY_MODE_MOD_OFDM 0 #define AR5K_PHY_MODE_MOD_CCK 1 #define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */ #define AR5K_PHY_MODE_FREQ_5GHZ 0 #define AR5K_PHY_MODE_FREQ_2GHZ 2 #define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */ #define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ #define AR5K_PHY_MODE_RAD_RF5111 0 #define AR5K_PHY_MODE_RAD_RF5112 8 #define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */ #define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */ #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */ For 10 MHz channels, AR5K_PHY_MODE_HALF_RATE needs to be set. There are also some information on madwifi-free : http://madwifi-project.org/browser/madwifi/trunk/ath_hal/ar5212/ar5212_reset.c I've not played myself with those bits, but that could be a good starting point for you. Regards, Benoit _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
