On Mon, Jul 26, 2010 at 3:29 PM, Matthew Garrett <mj...@srcf.ucam.org> wrote: > On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote: > >> What I meant was that the PCI config space would already have L1 >> enabled if L1 worked, so I don't see why we would need to nitpick out >> specifics here. All Atheros PCIE chips should work with L1. The advise >> given is to disable L0s though. I believe AR2425 would be one which >> likely had L0s enabled but requires it to be disabled. Not sure of >> others. But this is why I am saying this can be done globally for all >> ath5k chipsets. > > If L1 is set but the chip is pre-PCIe 1.1 then we'll disable L1 unless > the driver tells us that it's functional. The .inf from the Windows > driver seemed to suggest that only a subset of the chips re-enabled L1 > there, but if it's ok in general then that's a straightforward one-line > patch.
But why can't we just rely on what the device already has on its PCI config space and only ensure to disable L0s? Luis _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
