On 2011-11-02 7:16 PM, Daniel Golle wrote:
> On 11/02/2011 06:52 PM, Felix Fietkau wrote:
>>> I don't know the exact electronic details of the implementation, so I'd go
>>> with
>>> a list of known-to-be-good values (passed to the driver via platform-data)
>>> instead of a causal check (e.g. don't allow to set the TX and RX to the
>>> same
>>> antenna or whatever you imagine to possibly be an invalid setting).
>> I think passing such 'magic' values from user space to the driver is a
>> bad idea. The abstraction should happen within the driver and exposed
>> via the antenna control API.
> I agree that this should be abstracted away from the user.
> You reckon the user should set the values via
> iw phy phy0 set antenna 1 2
> -> set (0x09a0,0x0210)
> and
> iw phy phy0 set antenna 2 1
> -> set (0x0a90,0x0120)
> and let the driver know that only (1,2) and (2,1) are valid settings?
>
> it'd be nice to (additionally?) implement
> iw phy phy0 set antenna horizontal
>
> i would then imagine something like
> struct ath9k_platform_switchcom_profile {
> char *name;
> u16 tx_antenna;
> u16 rx_antenna;
> }
>
> and extend ath9k_platform_data by
> u8 um_switchcom_profiles;
> ath9k_platform_switchcom_profile *profiles;
>
> As available_anntenas_rx and available_anntenas_tx are just bitmasks for now,
> this first of all requires a way to handle the information about available
> antenna-combinations in struct wiphy. (right?)
The chip has 4 external bits which can be used to drive an antenna
switch. I'm currently looking at the details of the AR_PHY_SWITCH_COM
register - it controls the values of those 4 bits based on its internal
antenna selection state.
Idle: 0x0000000f
Transmit ant1: 0x000000f0
Transmit ant2: 0x00000f00
Receive ant1, LNA1: 0x0000f000
Receive ant2, LNA1: 0x000f0000
Receive ant1, LNA2: 0x00f00000
Receive ant2, LNA2: 0x0f000000
Receive ant1+ant2: 0xf0000000
So the difference between those two AR_PHY_SWITCH_COM values is that
they swap the antenna switch bits for antenna1 vs antenna2 (other
settings and combinations seem to be undefined).
To figure out the remaining settings for this hardware, please give me
the values of registers 0x99ac (AR_PHY_MULTICHAIN_GAIN_CTL) and 0xA208
(AR_PHY_CCK_DETECT) on your device.
- Felix
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