sbjaerum;141636 Wrote: > Sean, these are impressive plots. Can you share with us some details on > how you have designed the jitter suppression when receiving digital > input from an external source? > (I understand from your plots and explanation that you are not using > asynchronous sample rate conversion.)
There is no resampling or special buffering going on, although its possible this could be done in software later. Using separate linear supplies for each chip along the clock path (ak4113 receiver and the cpld), guard traces around those signals, and proper ground layout, all help to keep it clean. It won't reject unlimited amounts of jitter from the input though. > > Also, how is the word clock output mode working? > There is no dedicated word clock output connector. Are the word clock > signal instead sent to all the SPDIF/AES output connectors? > Correct. -- seanadams ------------------------------------------------------------------------ seanadams's Profile: http://forums.slimdevices.com/member.php?userid=3 View this thread: http://forums.slimdevices.com/showthread.php?t=28126 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
