On Tue, 2019-05-21 at 17:56 +0200, Ahmad Fatoum wrote: > From: Philipp Zabel <p.za...@pengutronix.de> > > Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk > tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to > enter the ldb_di_ipu_div divider. If the divider gets locked up, no > ldb_di[x]_clk is generated, and the LVDS display will hang when the > ipu_di_clk is sourced from ldb_di_clk. > > To fix the problem, both the new and current parent of the ldb_di_clk > should be disabled before the switch. As this can not be guaranteed by > the clock framework during runtime, make the ldb_di[x]_sel muxes read-only. > A workaround to set the muxes once during boot could be added to the > kernel or bootloader. > > Signed-off-by: Philipp Zabel <p.za...@pengutronix.de> > Signed-off-by: Fabio Estevam <fabio.este...@nxp.com> > Signed-off-by: Shawn Guo <shawn...@kernel.org> > [afa: ported from Linux kernel commit 03d576f202] > [afa: added exception for i.MX6QP, see kernel commit f4a0a6c309] > [afa: added cpu_has_err009219 helper function] > Signed-off-by: Ahmad Fatoum <a.fat...@pengutronix.de>
Reviewed-by: Philipp Zabel <p.za...@pengutronix.de> regards Philipp _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
