At least on RK3588 the dwcmshc core doesn't have an internal clock divider, we fully rely on the clock tree to configure the MMC clock. By default the clock comes from the 24MHz oscillator. For higher MMC clocks we have to reparent to a PLL clock, but if we do this once the 6bit divider iss not enough to scale down to the 400kHz MMC initialization clock. This means we must dynamically reparent the clock. This series adds support for finding the best divider/mux combination for composite clocks.
This series also adds some fixes to the dwcmshc driver which used to timeout on writing sometimes. Signed-off-by: Sascha Hauer <[email protected]> --- Sascha Hauer (6): mci: sdhci: rockchip: set hidspd before re-enabling the clock mci: sdhci: rockchip: disable clock while setting DLL mci: sdhci: rockchip: Wait for transfer complete interrupt with MMC_RSP_BUSY cmd mci: sdhci: rockchip: Update pre-change delay for rockchip platform clk: composite: pick best parent for round_rate / set_rate mci: sdhci: rockchip: officially support HS200 drivers/clk/clk-composite.c | 110 ++++++++++++++++++++++++++++++----- drivers/mci/rockchip-dwcmshc-sdhci.c | 51 ++++++++++------ 2 files changed, 128 insertions(+), 33 deletions(-) --- base-commit: 019d102038a64e6b6e8f445cbfd2d15e68d0ec3f change-id: 20260507-rockchip-emmc-0e8c5097cf33 Best regards, -- Sascha Hauer <[email protected]>
