On 5/11/26 2:07 PM, Sascha Hauer wrote:
> Per SDHCI 3.0+, HOST_CONTROL2's UHS Mode Select is bits 0..2 (3 bits)
> and bit 3 is the 1.8 V Signaling Enable. The current SDHCI_CTRL_UHS_MASK
> of GENMASK(3, 0) is one bit too wide and clears 1.8 V signaling every
> time sdhci_set_uhs_signaling() runs.
>
> Shrink the mask to GENMASK(2, 0) and add SDHCI_CTRL_VDD_180 = BIT(3) so
> controllers that need to drive 1.8 V on I/O for HS200/HS400/UHS modes
> can OR the bit in without it being clobbered on the next set_clock().
>
> No functional change for controllers where VDD_180 was unused (most
> in-tree drivers do not touch it; voltage switching there is either
> fixed by board wiring or handled by an external regulator).
>
> Assisted-by: Claude Opus 4.7 <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
Reviewed-by: Ahmad Fatoum <[email protected]>
> ---
> drivers/mci/imx-esdhc-common.c | 2 --
> drivers/mci/sdhci.h | 3 ++-
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mci/imx-esdhc-common.c b/drivers/mci/imx-esdhc-common.c
> index 050621d7fb..eb6a71915f 100644
> --- a/drivers/mci/imx-esdhc-common.c
> +++ b/drivers/mci/imx-esdhc-common.c
> @@ -12,8 +12,6 @@
>
> #define ESDHC_CTRL_D3CD 0x08
>
> -#define SDHCI_CTRL_VDD_180 0x0008
> -
> #define ESDHC_MIX_CTRL 0x48
> #define ESDHC_MIX_CTRL_DDREN (1 << 3)
> #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
> diff --git a/drivers/mci/sdhci.h b/drivers/mci/sdhci.h
> index 8d21febd7a..a04eb5b7ed 100644
> --- a/drivers/mci/sdhci.h
> +++ b/drivers/mci/sdhci.h
> @@ -132,13 +132,14 @@
> #define SDHCI_SIGNAL_ENABLE 0x38
> #define SDHCI_ACMD12_ERR__HOST_CONTROL2 0x3C
> #define SDHCI_HOST_CONTROL2 0x3E
> -#define SDHCI_CTRL_UHS_MASK GENMASK(3, 0)
> +#define SDHCI_CTRL_UHS_MASK GENMASK(2, 0)
> #define SDHCI_CTRL_UHS_SDR12 0x0
> #define SDHCI_CTRL_UHS_SDR25 0x1
> #define SDHCI_CTRL_UHS_SDR50 0x2
> #define SDHCI_CTRL_UHS_SDR104 0x3
> #define SDHCI_CTRL_UHS_DDR50 0x4
> #define SDHCI_CTRL_HS400 0x5 /* Non-standard */
> +#define SDHCI_CTRL_VDD_180 BIT(3)
> #define SDHCI_CTRL_DRV_TYPE_MASK GENMASK(5, 4)
> #define SDHCI_CTRL_DRV_TYPE_B 0x0000
> #define SDHCI_CTRL_DRV_TYPE_A 0x0010
>
--
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