"You have 100% full control over anything the PRU can access." This pru code seems to disproves this. The PRU cannot modify the configuration registers.
// enable ocp master. LBCO r0, C4, 4, 4 CLR r0, r0, 4 SBCO r0, C4, 4, 4 // turn on gpio mov r1, 0x4000 mov r0, 0x44E07194 SBBO b, a, 0, 4 // readback LBBO b, a, 0, 4 // gpio off mov b, 0x4000 mov a, 0x44E07190 SBBO b, a, 0, 4 // readback LBBO b, a, 0, 4 On Monday, May 19, 2014 2:36:51 PM UTC-7, Charles Steinkuehler wrote: > > On 5/19/2014 4:06 PM, Brandon I wrote: > > The pin mux registers require privileged memory access, which is why > > the kernel space is usually required. The pru can write these!? > > Of course. The PRU is directly wired into the on-chip bus, and bypasses > all ARM side sanity checks like memory page access restrictions. You > have 100% full control over anything the PRU can access, which is just > about every significant chunk of hardware on the die except for: > > * SGX-530 GPU > * AES & SHA crypto accelerator > * USB > * MMC > > Details are in the Interconnects section of the TRM (section 10), and > remember: > > With great power comes great responsibility! > > -- > Charles Steinkuehler > cha...@steinkuehler.net <javascript:> > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
