On 1/3/2016 7:53 AM, Thomas Köhler wrote: > > Any help? So many thanks... I hope the problem can be understood.
Unless you carefully write kernel code to treat your DDR memory buffer as DMA memory, you are almost certainly encountering caching effects. The ARM core reads the memory location once, and will not do so again as long as the data remains in the cache. The more often you read the DDR memory location, the more likely the data is to stay in the cache. I recommend instead of using a buffer in DDR memory, use the PRU data memories. They are accessible by both the ARM and PRU cores, and have the proper memory flags setup so the ARM core will not cache reads. -- Charles Steinkuehler char...@steinkuehler.net -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
