I wonder how much sophisticated resource scheduling regarding C66x DSP cores 
can be. For example, i estimated that code of my project's software would need 
at least 2 cores' entire processing capacity (according to TI documentation) to 
be able to work in hard real-time. But then i have so much untapped processing 
power that can be used by third party plugins. Can i partition workload on 
DSP's like in generic-purpose CPU? 

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