So what is the maximum latency to can tolerate?

Remember, each DSP has 8 functional units (two multiply units and 6 ALUs) which 
means you can execute up to 8 instructions per cycle.

Here are some core benchmarks:

http://www.ti.com/lsds/ti/processors/technology/benchmarks/core-benchmarks.page 
<http://www.ti.com/lsds/ti/processors/technology/benchmarks/core-benchmarks.page>



Regards,
John




> On Jun 26, 2017, at 9:34 PM, MDX <speedy1...@gmail.com> wrote:
> 
> Well, samples are part of stream that must "return" to output in-order and 
> with a minimal latency, and i never planned to use asm
> 
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