BTW, you mentioned moving to Zynq, but that processor is more expensive than 
the complete BBB. Zynq eval boards or kits are even more expensive, not to 
mention the cost of tools, etc. One other problem is the learning curve is very 
steep if you want to take advantage of the FPGA features. Anyway, the 
applications for Zynq and BBB are completely different. I know, because I have 
looked at the possibility of using Zynq over the years and each time, I have 
given it a pass. 

I’m currently using PSOC6 (CortexM4 and CortexM0) for some of my projects (no 
Linux, using FreeRTOS) and it has a Verilog programmable frontend, which is 
much easier to learn. 

Regards,
John





> On Oct 16, 2018, at 3:49 PM, 'Peter Armbrüster' via BeagleBoard 
> <beagleboard@googlegroups.com> wrote:
> 
> Great!
> Thank you very much.
>  
> Best wishes
>  
> Peter.
>  
>  
>  
> Von: beagleboard@googlegroups.com [mailto:beagleboard@googlegroups.com] Im 
> Auftrag von John Syne
> Gesendet: Mittwoch, 17. Oktober 2018 00:41
> An: beagleboard@googlegroups.com
> Betreff: Re: [beagleboard] Using SPI in a kernel module
>  
> From what I read, TI are no longer maintaining Starterware, but there is a 
> community driven development on Sourceforge:
>  
> https://sourceforge.net/projects/starterwarefree/ 
> <https://sourceforge.net/projects/starterwarefree/>
>  
> 
> Regards,
> John
>  
>  
>  
> 
> 
> 
>> On Oct 16, 2018, at 4:47 AM, Gerhard Hoffmann <g...@hoffmann-hochfrequenz.de 
>> <mailto:g...@hoffmann-hochfrequenz.de>> wrote:
>>  
>>  
>>  
>> Am 16.10.2018 um 10:38 schrieb true-t...@web.de <mailto:true-t...@web.de>:
>>> Hi John, 
>>>  
>>> i try to drive the BBB McSPI with using the Pru.
>>> Maybe you can help me to find your tip:"If you look on Github, the 
>>> Starterware examples have been ported to the PRU".
>>> Lot of thanks
>>>  
>> 
>> I have the very same problem. If you google around, you find sometimes some 
>> factoids, and that is
>> usually stuff like
>> 
>> /* SPIEN line is forced to low state.*/
>> McSPICSAssert(SOC_SPI_0_REGS, chNum);
>> 
>> /* Enable the Tx/Rx interrupts of McSPI.*/
>> McSPIIntEnable(SOC_SPI_0_REGS, MCSPI_INT_TX_EMPTY(chNum) |
>>                         MCSPI_INT_RX_FULL(chNum));
>> 
>> /* Enable the McSPI channel for communication.*/
>> McSPIChannelEnable(SOC_SPI_0_REGS, chNum);
>> 
>> Abstraction & insight gained == 0. Just repetition.
>> 
>> This all floats in the middle of nowhere. Guess where the header files are
>> or where some values hit some registers.
>> If you search on, you end up at a frozen Wiki or a locked discussion thread.
>> 
>> It seems, TI has given up on the Sitara. Maybe it is time to move on to Zynq.
>> 
>> regards, Gerhard
>> 
>> 
>> 
>> 
>> 
>> 
>>  
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