---- Original Message ----
From: David Christensen <dpchr...@holgerdanske.com>
To: beginners@perl.org
Cc: Soham Das <soham...@yahoo.co.in>
Sent: Sunday, 12 July, 2009 10:39:08 AM
Subject: RE: Perl for HDL Verification
Soham Das wrote:
> Can anyone who has worked in Hardware Designing domain, particularly
> HDL and RTL design, tell me how exactly is Perl used to generate
> testbenches and verification work.
I used Perl for testing Verilog designs back in ~2002. Going from memory, I
wrote my designs and test benches in Verilog, had the test benches generate
"ok"/ "not ok" messages, wrote *.t Perl scripts to run each design/ test bench
through the Verilog simulator (Icarus), and wrote a top-level Perl script that
used Test::Harness to process the *.t scripts. I can't remember if the "1..N"
messages were in the test bench or the *.t script. But, it worked great! :-)
Thank You!
But isn't Perl used to generate those testbench scripted in Verilog? This is
what I had an impression of.
And is it possible to run Perl scripts using iVerilog.
I think most of what I am talking doesnt make much sense, because I am a bit
new to Perl, and even newer to automated testing.
Soham
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