Hi Jonathan, > On Aug 4, 2021, at 20:28, Jonathan Morton <chromati...@gmail.com> wrote: > > I firmly believe this is due to an I/O bottleneck in the SoC between > the network complex and the CPU complex, not due to any limitation of > the CPU itself. It stems from the reliance on accelerated forwarding > hardware to achieve full line-rate throughput. Even so, I'd much > rather have 40Mbps with Cake than 400Mbps with a dumb FIFO. (Heck, > 40Mbps would be a big upgrade from what I currently have.) I think > some of the newer Atheros chipsets are less constrained in this > respect. > > There are two reasonably good solutions to this problem in the hands > of the SoC vendors: > > 1: Relieve that I/O bottleneck, so that the CPU can handle packets at > full line rate. I assume this is not hugely complicated to implement, > and just requires a sufficient degree of will to select the right > option from the upstream fabless IP vendor's design library. > > 2: Implement good shaping, FQ, and AQM within the network complex. At > consumer broadband/LAN speeds, this shouldn't be too difficult (unlike > doing the same at 100+ Gbps), but it does require a significant amount > of hardware design and validation, and that tends to have long lead > times. > > There is a third solution in the hands of us mere mortals: > > 3: Leverage the Raspberry Pi ecosystem to build a CPE device that > meets our needs. This could be a Compute Module 4 (which has the > necessary I/O throughput) mounted on a custom PCB that provides > additional Ethernet ports and some reasonable Wifi AP. It could > alternatively be a standard Pi 4B with some USB Ethernet and Wifi > hardware plugged into it. Either will do the job withhout any > Ethernet bottlenecks, although the capabilities of USB Wifi dongles > are usually quite limited.
Have a look at https://www.dfrobot.com/product-2242.html, which is a small carrier for the raspberry pi4 compute module that offers two gigabit ethernet ports, the one from the CM and an additional RTL81111 one connected via the PCIe lanes. At $45 it is a bit pricy, but it sure is small and elegant. People on the OpenWrt Forum report traffic shaping at 1Gbps rates without overloading the CPUs (this needs minimal configuration for receive side packet steering, otherwise all network IRQ and qdisc processing sticks to CPU0, in which case shaping does not reach Gbps speeds, at least not for bi-directonal traffic). That still leaves the need for an AP and a switch (one might be able to "abuse" an AP for switch ports if in a pinch). Regards Sebastian > > - Jonathan Morton _______________________________________________ Bloat mailing list Bloat@lists.bufferbloat.net https://lists.bufferbloat.net/listinfo/bloat
