On Mon, Apr 15, 2013 at 11:09 AM, Greg London <em...@greglondon.com> wrote:
[...]
> So, I've been doing verilog testbenches for years,
> system verilog test benches for years, and they all
> have their limtations as not being what I would call
> a "real" language. So, I'm trying to write a testbench
> in C++, interface it with "C", use that to jump the DPI
> barrier to verilog, and tie into the hardware simulation.
>
> So, I'm limited to c/c++ because we're tied to hardware
> simulators which can only run hardware languages such
> as verilog/vhdl and can only interface to one software
> language, namely c, which can then tie into c++.
>
> That is, at the moment, my only option for any testbench
> that isn't written in verilog or vhdl. The simulator
> limits me to c and c++.
I'm writing some C++ at the moment that fits into the first group
(performance-critical code). For unit testing I've been emitting TAP
protocol and testing it with prove, but are there better approaches?
I get a test file with a lot of code that looks like this:
printf(
"%s %d: Some useful description and maybe a number %d\n",
(expected_value == test_value) ? "ok" : "not ok", ++tests,
some_useful_debugging_info
);
I find it manageable, but I'm wondering about the next guy.
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