#2004: sparc64: problem using softint and timer together
--------------------+-----------------------
Reporter: gedare | Owner: gedare
Type: defect | Status: accepted
Priority: normal | Milestone: 4.11.1
Component: bsps | Version: HEAD
Severity: normal | Resolution:
Keywords: |
--------------------+-----------------------
Changes (by gedare):
* status: assigned => accepted
* milestone: 4.11 => 4.11.1
Old description:
> sparc64 hardware shares an interrupt level (14) between tick comparison
> and software-raised interrupts. current bsps do not handle the situation
> of both interrupt sources simultaneously, so software interrupts cannot
> be used when the timer also is used. What happens is the interrupt level
> (PIL) does not get set/reset properly and interrupts are missed.
>
> The attached patch is a work-around that hacks the clock isr, but I need
> to look more closely at the generic ISR handling code to see if the bug
> is due to interactions between PIL assignment, interrupt enable/disable,
> and scheduling.
New description:
sparc64 hardware shares an interrupt level (14) between tick comparison
and software-raised interrupts. current bsps do not handle the situation
of both interrupt sources simultaneously, so software interrupts cannot be
used when the timer also is used. What happens is the interrupt level
(PIL) does not get set/reset properly and interrupts are missed.
The attached patch is a work-around that hacks the clock isr, but I need
to look more closely at the generic ISR handling code to see if the bug is
due to interactions between PIL assignment, interrupt enable/disable, and
scheduling.
--
Comment:
Bumping milestone to post 4.11 release. I suspect the patches I posted can
just be applied though.
--
Ticket URL: <http://devel.rtems.org/ticket/2004#comment:5>
RTEMS Project <http://www.rtems.org/>
RTEMS Project
_______________________________________________
bugs mailing list
bugs@rtems.org
http://lists.rtems.org/mailman/listinfo/bugs
