Gedare Bloom commented on a discussion on cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1239#note_149903 > + __asm__ volatile ( "fence " #pred ", " #succ : : : "memory" ) > + > +static inline void _RISCV_data_barrier( void ) > +{ > + _RISCV_FENCE( rw, rw ); > +} > + > +static inline void _RISCV_MMIO_store_release_fence( void ) > +{ > + _RISCV_FENCE( o, i ); > +} > + > +#if defined(RISCV_USE_S_MODE) > +static inline void _RISCV_TLB_flush_all_entries( void ) > +{ > + __asm__ volatile ( "sfence.vma zero, zero" ); This is a different instruction menmonic. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1239#note_149903 You're receiving this email because of your account on gitlab.rtems.org.
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