Issue created by Wayne Thornton:
https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5644
## Description:
We have introduced a new Super Core architecture hook, `_CPU_Spin_wait()`, to
mitigate aggressive speculative execution penalties, reduce thermal load, and
lower bus contention during SMP spin-wait polling loops. The reference template
is currently documented in `cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h`
and natively implemented for `x86_64` upon merging of rtems/rtos/rtems!1256.
The riscv architecture port needs to override the default fallback by
implementing a native inline assembly pipeline throttle in
`cpukit/score/cpu/riscv/include/rtems/score/cpu.h`.
## Suggested Implementation:
For RISC-V targets supporting the `Zihintpause` extension (or standard
unassigned HINT space), this should utilize the `pause` instruction paired with
a compiler memory clobber. Because `pause` is encoded as a FENCE hint
(`0x0100000F`), it backwards-compatibly executes as a `nop` on legacy cores
that do not implement the extension:
```
static inline void _CPU_Spin_wait( void )
{
__asm__ volatile( "pause" ::: "memory" );
}
#define _CPU_Spin_wait _CPU_Spin_wait
```
If older toolchains reject the "`pause`" mnemonic, the raw instruction hint
`.word 0x0100000F` or `.insn` equivalent may be evaluated.
## Verification:
Validate that the implementation compiles cleanly and passes the standalone SMP
spin-wait test suite: `testsuites/smptests/smpspinwait01`. Once defined, the
preprocessor will automatically override the temporary test-level fallback in
`init.c`.
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