Issue created by Wayne Thornton: 
https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5646



## Description:
We have introduced a new Super Core architecture hook, `_CPU_Spin_wait()`, to 
mitigate aggressive speculative execution penalties, reduce thermal load, and 
lower bus contention during SMP spin-wait polling loops. The reference template 
is currently documented in `cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h` 
and natively implemented for `x86_64` upon merging of rtems/rtos/rtems!1256.

The powerpc architecture port needs to override the default fallback by 
defining this interface in `cpukit/score/cpu/powerpc/include/rtems/score/cpu.h`.

Suggested Implementation:
On SMT-capable PowerPC cores (such as e6500 or POWER8/POWER9), thread priority 
hints can be used to yield processor execution cycles to sibling hardware 
threads (e.g., setting low thread priority via `or 1,1,1` or `or 27,27,27`, 
followed by restoring medium priority `or 2,2,2`). For generic PowerPC builds 
where SMT hints are unsupported, explicitly apply the compiler barrier:

```
static inline void _CPU_Spin_wait( void )
{
  /* Add architecture-specific thread priority yield hints if supported by 
target CPU model */
  RTEMS_COMPILER_MEMORY_BARRIER();
}
#define _CPU_Spin_wait _CPU_Spin_wait
```

## Verification:
Validate that the implementation compiles cleanly across standard PowerPC SMP 
targets and passes the standalone SMP spin-wait test suite: 
`testsuites/smptests/smpspinwait01.` Once defined, the preprocessor will 
automatically override the temporary test-level fallback in `init.c`.

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