Issue created by Sebastian Huber: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5688
The interrupt level of the MIPS port and the interrupt controller of the `jmr3904` BSP have several defects. The port does not treat level zero as "enable all", it derives the level from the wrong status register bits, and it takes the vector base from the wrong place. The interrupt mask of the BSP is not visible where the port needs it. The BSP has no interrupt controller at all, so the interrupt manager cannot enable, disable or raise a vector, and the processor interrupt sources stay unmasked. Found while running the full test suite on the GDB simulator. This description was created with Claude Code assistance. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5688 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/sent_notifications/5-8f788p315jq6i4t1v1h2qqgk6-1d/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
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