Matteo Concas commented: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5755#note_158891 The GRISCV system does not exist and I'm not sure it can exist. It expects an IRQMP controller (which is only used in SPARC systems) with a NOEL core which by defaults will come with a PLIC/CLINT for interrupts. It's possible you could make a design like it but it would require a lot of VHDL hacking I don't know why anyone would. So I do not think it is wise to sink anymore time into supporting this BSP. -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5755#note_158891 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/sent_notifications/5-e28ahu1l0rknf7o4ut7c38dii-1d/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
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