Issue created by Sebastian Huber: 
https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5768



`_ISR_Handler` of `cpukit/score/cpu/mips/cpu_asm.S` saves the status
register of the interrupted context into the frame at `R_SR`. The
common exit, `_ISR_Handler_exit`, never restores it. Only the path
which calls `_Thread_Dispatch()` builds a status register of its own.

A handler which changes the register therefore keeps the change after
the return. `_Terminate()` clears the interrupt enable before it calls
the fatal error extensions, because it does not expect to return. An
extension which leaves the fatal error with a `longjmp()` escapes with
the interrupts of the processor disabled, and the return of the
interrupt leaves them so.

`ts-validation-intr` does exactly that.
`BspReqInterruptHandlerDispatchUnchecked` wraps
`bsp_interrupt_handler_default()`, takes the fatal error of a vector
with no entry and returns through `longjmp()`. The first action of the
case reaches the wrapped handler. Every later action raises the
software interrupt of `mips/malta`, which stays pending and unmasked,
because the enable of the processor is off. The case waits for an
interrupt which cannot arrive.

At the stall the cause register holds `0x00000100` and the status
register holds `0x20000100`, so `IP0` is pending and `IM0` is
unmasked while `IE` is clear. The nest level of the interrupt and the
dispatch disable level are both zero, so the system is in ordinary
task context.

Restore the status register of the frame in `_ISR_Handler_exit`. The
path which dispatches a thread builds its own value, so the change
needs care where the two meet.

Found in the repair of the Malta BSP for the test suite. This
description was created with Claude Code assistance.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/work_items/5768
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