Jiri Gaisler created a merge request: https://gitlab.rtems.org/rtems/tools/rtems-sis/-/merge_requests/16
Project:Branches: jirigaisler/rtems-sis:gdb to rtems/tools/rtems-sis:main Author: Jiri Gaisler ## Summary ``` I was bringing up real Griscv hardware, and these issues came up when simulating the testbenches on sis: func.c: go and tgo command would not start timer properly (The run and go commands could now in fact be merged.) remote.c: gdb remote stub did not detect griscv target Griscv has a strange mix of cputype=leon3 and archtype=riscv riscv.c: terminate sim on riscv ebreak instruction This is to play nicely with Gaisler's NCC tool-chain Also, announce supported IMAFDC extensions in the MISA csr. riscv.c: send only integer registers to gdb sis-riscv is not able to announce FPU support to gdb, so sending FPU registers will break the remote-gdb protocol. ``` ## Generative AI <!--If you have used AI please use the "AI Contribution" template otherwise leave this blank see our fulls statement at https://www.rtems.org/generative-ai/--> <!--Default settings, if it is a dropdown it will set after submission--> -- View it on GitLab: https://gitlab.rtems.org/rtems/tools/rtems-sis/-/merge_requests/16 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/namespace/15/sent_notifications/6-9ghcqogg6o99bdldeqw497olh-f/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
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