Sam Price started a new discussion on bsps/riscv/esp32/start/bspstart.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1555#note_161780 > + */ > RTC_WRITE( RTC_CNTL_SW_CPU_STALL_REG, 0 ); > > - /* Disable timergroup 0 watchdog */ > + /* > + * Timer group 0's watchdog follows the same procedure as the RTC > watchdog, > + * with its own key register. Its configuration registers are updated > + * asynchronously, so the change only takes effect once > + * TIMG_WDT_CONF_UPDATE_EN is written (register 11.10). > + */ > + TIMG_WRITE( TIMG_WDTWPROTECT_REG, WDT_WKEY_VALUE ); > timg_wdtconfig0 = TIMG_READ( TIMG_WDTCONFIG0_REG ); > - TIMG_WRITE( TIMG_WDTCONFIG0_REG, timg_wdtconfig0 & TIMG_WDTCONFIG0_EN ); > + TIMG_WRITE( > + TIMG_WDTCONFIG0_REG, > + timg_wdtconfig0 & ~( TIMG_WDTCONFIG0_EN | TIMG_WDT_FLASHBOOT_MOD_EN ) **Reference code for timer group 0's watchdog.** ESP-IDF's bootloader, [`bootloader_config_wdt()`](https://github.com/espressif/esp-idf/blob/0e6b480f858c69862ffb6001d96e9eef74599a6e/components/bootloader_support/src/bootloader_init.c#L104-L111), unlocks MWDT0, clears flash-boot mode and locks again. This BSP also clears the enable bit. The register read back on hardware as `0x0004c000`, enable already clear, so clearing it changes nothing on this part but doesn't depend on the ROM's state. Zephyr's no-bootloader path calls the equivalent [`config_wdt()`](https://github.com/zephyrproject-rtos/zephyr/blob/d1b8eec76bfd14058854245d09aa1e413e355c4a/soc/espressif/esp32c3/hw_init.c#L91). -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1555#note_161780 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/namespace/49/sent_notifications/6-2v77lz6dwcyy8hi7ej0kcel4m-1d/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
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