Hi Laura: When I set the sample time of sine wave to 1/8, all outputs are still same. I look at the subsystem of ADC module, and I find, except O1 has 1 more cycle delay, all other channel have same function. I am not sure how the ADC is implement. Do you have any idea?
Thanks Wan ________________________________ From: Laura Spitler [mailto:laura.spit...@gmail.com] Sent: Wednesday, 29 October 2008 12:15 PM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berkeley.edu Subject: Re: [casper] Casper 10.1 library issue Hi Wan, In the Simulink 'Sine Wave' block, do you have your sample time set to 1/8 or 1? Similarly if you turn interleave off, the sample time should be 1/4. Best, Laura On Tue, Oct 28, 2008 at 8:59 PM, <wan.ch...@csiro.au> wrote: Hi All: I just set a simple ADC module in simulink and check the ADC output. But the issue is that all eight outputs have same output data. This is different with showed in manual. From manual, these output should generate 8 sequence sampling. But as I know, they seems same. For details, please see the attached. Any idea? Thanks Wan
