hi homin,
the 16 input FFT takes twice as many resources as an 8 input FFT.
(the 16 input FFT has 16 parallel inputs so it can compute fft's at 16
times the fpga clock rate).
this factor of two expansion in fpga resources is largely independent of
the input
data bit width, because almost all the computation in the FFT is done
with 18 bit
arithmetic, independent of the data input bit width.
a few years ago, dave macmahon developed a "bit growth" biplex FFT that
grows the number of bits each butterfly stage. eg: if you start with 4
bit data,
and do a 1K FFT, you need 10 stages - the first stage is done with 4 bit
precision,
then 5 bits, then 6 bits....., then 13 bit precision in the last
stage. this bit growth
is needed to accomodate dynamic range increase as one goes from time to
frequency
domain.
you could use dave's biplex bit growth FFT in the 16 input FFT (since
the 16 bit FFT
is largely made of biplex FFT's), and this will save FPGA resources.
best wishes,
dan
On 7/7/2010 8:10 PM, homin jiang wrote:
Dear all:
I am developing the 5G adc board. I am feeding 16 ports with 4 bits from
ADC block to PFB and FFT after finished the test of 8 ports with 8 bits.
In my previous test of 8 ports with 8 bits, i have compiled the 2K
channels , 8 taps model successfully under normal Windows without 3GB
options.
At this moment, i am forced to switch on the option of 3GB , also i have
to reduce the channel size to 1K, otherwise the Virtex 5 will explode.
Are there anyway to make the PFB and FFT more efficient to accommodate
the 16 ports input ? My thinking is 16x4 should be equal to 8x8,right ?
cheers
homin jiang
