On Jul 7, 2010, at 21:05 , Dan Werthimer wrote:
a few years ago, dave macmahon developed a "bit growth" biplex FFT
that
grows the number of bits each butterfly stage. eg: if you start
with 4 bit data,
and do a 1K FFT, you need 10 stages - the first stage is done with
4 bit precision,
then 5 bits, then 6 bits....., then 13 bit precision in the last
stage. this bit growth
is needed to accomodate dynamic range increase as one goes from
time to frequency
domain.
you could use dave's biplex bit growth FFT in the 16 input FFT
(since the 16 bit FFT
is largely made of biplex FFT's), and this will save FPGA resources.
My FFT is actually a "quadplex radix-4 FFT" rather than a "biplex
radix-2 FFT". It was developed for the ATA correlator and uses fewer
multipliers than an equivalent pair of biplex radix-2 FFTs, which was
necessary given the project's requirements and FPGA resources. It
has not been updated since the 7.1 toolflow and it also supports data
rate == fpga clock rate. It would take some additional work to
update it for the 10.1 (or beyond) toolflow and support data rate !=
fpga clock rate, but IMHO whoever did it would be very glad they
did. It really works nicely and, as Dan mentioned. it grows the bit
width as needed which can save yet more resources!
FWIW, it's available in the CASPER subversion repository (along with
some other nice blocks that I think have been ported to the 10.1
toolflow)...
http://casper.berkeley.edu/svn/trunk/newfft_library/
Enjoy,
Dave
