Hi everyone, I've been trying to get a design with DRAM to work on ROACH, and I'm having some difficulty with the CPU interface. The documentation on the wiki suggests that in order to write data into the DRAM that can be read out over the CPU interface, I need to skip certain values in the DRAM when writing, due to the narrower bus on the CPU interface.
I've had a little bit of trouble getting this to work though, so I was wondering if anyone has a demo design that writes (for example, a counter) to ROACH DRAM in a way that the consecutively written values can be read out in BORPH over the CPU interface? (I have seen Laura's DRAM demo design on the wiki, but as best I could tell that was not set up for CPU interfacing.) Thanks, Peter ________________________________________________ Message sent using GamCo WebMail
