Hi Laura, cc. everyone, Thanks very much. I think I was seeing 512 MB of DRAM, so this single- vs dual-rank DIMM story seems to explain what is happening.
Does anyone have recommendations for what single-rank 1GB DIMM I should buy? Has anyone had success using a single-rank 2GB DIMM to get 2GB of memory for the ROACH? If so, which ones do you recommend? (For example, would this work? http://www.newegg.com/Product/Product.aspx?Item=N82E16820139054 ) Thanks, Peter -----Original Message----- From: Laura Spitler [mailto:laura.spit...@gmail.com] Sent: Sunday, May 22, 2011 3:36 PM To: pe...@dotnet.za.net Cc: casper@lists.berkeley.edu Subject: Re: [casper] Sample design for ROACH DRAM and CPU Hi Peter, Unfortunately I don't currently have a way to look at the model, so I'm going to have to answer based off old emails and my memory. > This might useful for others too, hence the reply to the list: it seems that > if I use an address counter width of 25 bits in the demo design, I see > writes that are overlapped, but that if I use an address counter width of 24 > bits, then I don't see overlapped writes. I am using the "standard" RAM that > is shipped by Digicom on my ROACH, so I believe this is some variety of 1GB > DIMM. I think this means that only 256 MB, or perhaps 512 MB, of the RAM is > being addressed. There are likely two issues at work. One is the ROACH DRAM controller (last I heard from David George) only works with single rank DIMMs, and the "standard" 1 GB ROACH DIMMs are dual rank. This means you can only address have the memory. The second is a minor bug in the "mlib_devel_10_1/xps_lib/XPS_ROACH_base/pcores/dram_controller_v1_00_a/hdl/v erilog/dram_controller.v" file. The parameter ROW_WIDTH should be 14, not 13. This should be fixed, but maybe check your version. > > The DRAM documentation on the wiki suggests that bit 27 of the address is > ignored, but that bits 28 and 29 are valid. I am curious about which > circumstances would cause the bitwidth-25 counter (whose most significant 24 > bits are fed into the DRAM block) to result in a wrap-around. Is this > because the module I have actually has bit 23 disabled? What is known about > the addressing for the default DIMM modules that Digicom ships the boards > with? I think you're reading the BEE2 documentation. For the ROACH addressing only look at "ROACH specific Info". Laura > > Thanks in advance. > > Cheers, > Peter > > -----Original Message----- > From: Laura Spitler [mailto:laura.spit...@gmail.com] > Sent: Friday, May 20, 2011 11:40 AM > To: Peter > Cc: casper@lists.berkeley.edu > Subject: Re: [casper] Sample design for ROACH DRAM and CPU > > Hi Peter, > > I just uploaded to the Wiki a design Jason Manley made that writes a > counter into to the DRAM taking into account the narrower bus on the > CPU interface. It should clarify things for you. > > (Jason, let me know if you object to me uploading this design.) > > Cheers, > Laura > > > On Fri, May 20, 2011 at 2:12 PM, Peter <pe...@dotnet.za.net> wrote: >> Hi everyone, >> >> I've been trying to get a design with DRAM to work on ROACH, and I'm > having >> some difficulty with the CPU interface. The documentation on the wiki >> suggests that in order to write data into the DRAM that can be read out > over >> the CPU interface, I need to skip certain values in the DRAM when writing, >> due to the narrower bus on the CPU interface. >> >> I've had a little bit of trouble getting this to work though, so I was >> wondering if anyone has a demo design that writes (for example, a counter) >> to ROACH DRAM in a way that the consecutively written values can be read > out >> in BORPH over the CPU interface? >> >> (I have seen Laura's DRAM demo design on the wiki, but as best I could > tell >> that was not set up for CPU interfacing.) >> >> Thanks, >> Peter >> >> >> >> ________________________________________________ >> >> Message sent >> using GamCo WebMail >> >> >> > >
