Hi, Andrew, Thanks for looking into this.
On Dec 6, 2012, at 12:40 AM, Andrew Martens wrote: > Just done some sims and can't replicate the behaviour. Interesting. I just did some sims and also can't replicate this behavior in simulation. > Your problem is therefore interesting. Is this with ROACH2 or ROACH1? > What version of tools (and library) are you compiling with? Do all the > snapshot blocks in your design exhibit this behaviour? When you say they > are triggered, do you mean that the byte count in increasing, or does > the busy bit just go high? (which is expected). Do the snapshot blocks > stop capturing as expected? I am working on ROACH2. I am using the snapshot block from mlib_devel commit fd0e4c6. I am using 13.3 of the Xilinx tools up until the "EDK/ISE/Bitgen" step which I run manually using version 14.2 of the Xilinx tools. Yes, all snapshot blocks in my design exhibit this behavior. When I say they are triggered, I mean that the contents of the BRAM change immediately upon writing 5 to the ctrl register while the trigger input is 0 (i.e. before I set the trigger to 1). Yes, they stop capturing as expected. This is part of a design I am using for developing the ADC16 yellow block, so it's entirely possible that I'm doing something bad that is causing the snapshot block to misbehave. I'll debug further on my end and report back. Thanks again, Dave
