> Hi Louis, > > > I have the same problem of "roach & adc sampling rate". We want to use > ROACH as a holography correlator,but the sampling frequency is too high. > After we reset the MSSGE block clock rate to 50 MHz, and also used the > method you have been used(change all of the instances of 'HIGH' to 'LOW'in > the file of > XPS_ROACH_base/pcores/adc_interface_v1_01_a/hdl/vhdl/adc_interface.vhd), > but the bee_xps always complain a error. > > > The ADC we used is a 2*1000-8 one. The ADC sampling rate we want to use is > 80MHz, so the FPGA clock is 20MHz. Is there any lower limit for the ROACH > clock rate?(same question)
I don't know the numerical answer, but I think there is a lower limit because of the clock manager settings. Can you not just sample faster and decimate as the first stage of your processing? John > > > Best, > Peixin > > > > -- > > ========================================== > ÅáöÎ (Xin Pei) > > Öйú¿ÆѧԺн®ÌìÎĄ̈ > Xinjiang Astronomical Observatory, CAS > > н®ÎÚ³ľÆëÊпÆѧһ½Ö150ºÅ (Óʱà: 830011) > 150, Science 1-Street > Urumqi, Xinjiang 830011 > China > > µç»°(Tel): +86-(0)991-3689068 > ´«Õæ(Fax): +86-(0)991-3838628 > ========================================== > > >
