Hello Peixin,
Sorry for taking so long to respond to this. I ended up doing
what John suggested; I just sampled faster at a rate that the ROACH was more
comfortable with and decimated appropriately.
> -- Louis P. Dartez
> (956) 372-5812
> Graduate Research Assistant
> Center for Advanced Radio Astronomy
> University of Texas at Brownsville
On Jun 5, 2013, at 8:34 AM, John Ford <jf...@nrao.edu> wrote:
>> Hi Louis,
>>
>>
>> I have the same problem of "roach & adc sampling rate". We want to use
>> ROACH as a holography correlator,but the sampling frequency is too high.
>> After we reset the MSSGE block clock rate to 50 MHz, and also used the
>> method you have been used(change all of the instances of 'HIGH' to 'LOW'in
>> the file of
>> XPS_ROACH_base/pcores/adc_interface_v1_01_a/hdl/vhdl/adc_interface.vhd),
>> but the bee_xps always complain a error.
>>
>>
>> The ADC we used is a 2*1000-8 one. The ADC sampling rate we want to use is
>> 80MHz, so the FPGA clock is 20MHz. Is there any lower limit for the ROACH
>> clock rate?(same question)
>
> I don't know the numerical answer, but I think there is a lower limit
> because of the clock manager settings.
>
> Can you not just sample faster and decimate as the first stage of your
> processing?
>
> John
>
>>
>>
>> Best,
>> Peixin
>>
>>
>>
>> --
>>
>> ==========================================
>> ÅáöÎ (Xin Pei)
>>
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